diff options
| author | Mike Qiu <qiudayu@linux.vnet.ibm.com> | 2014-07-02 04:02:08 -0400 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2014-07-21 14:48:45 +1000 |
| commit | e3263abb512c80ca89e81d1ad9045dfd413188cb (patch) | |
| tree | 3dc7264219b707109704cac3dd830aefde53ede0 /include | |
| parent | 9cd97494117f86b84e8b946d025226035acff70e (diff) | |
| download | skiboot-e3263abb512c80ca89e81d1ad9045dfd413188cb.zip skiboot-e3263abb512c80ca89e81d1ad9045dfd413188cb.tar.gz skiboot-e3263abb512c80ca89e81d1ad9045dfd413188cb.tar.bz2 | |
PHB3: Support error injection
The patch implements phb3 backend to support error injection. For MMIO
and PCI-CFG error injection, we check the address is valid or not. The
address will be used for error injection if that's valid. Otherwise,
we have to figure one out from M32DT or RTT_TABLE.
As IO space isn't supported on PHB3, we're not going to support IO error
injection on PHB3.
All PEs have same DMA space. So we can't distinguish individual PE's
space and don't support DMA error injection for now. Perhaps we don't
understand how to do that. It needs more time for more investigation.
64-bits error injection will be supported later.
Signed-off-by: Mike Qiu <qiudayu@linux.vnet.ibm.com>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/phb3-regs.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/include/phb3-regs.h b/include/phb3-regs.h index 0aaab9a..2611b5f 100644 --- a/include/phb3-regs.h +++ b/include/phb3-regs.h @@ -135,9 +135,20 @@ #define PHB_IVC_UPDATE_Q_LSH PPC_BITLSHIFT(35) #define PHB_IVC_UPDATE_SID_MASK PPC_BITMASK(48,63) #define PHB_IVC_UPDATE_SID_LSH PPC_BITLSHIFT(63) -#define PHB_PAPR_ERR_INJ_CONTROL 0x2b0 +#define PHB_PAPR_ERR_INJ_CTL 0x2b0 +#define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) +#define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) +#define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) +#define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) +#define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) +#define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) +#define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 +#define PHB_PAPR_ERR_INJ_MASK_CFG_MASK PPC_BITMASK(4,11) +#define PHB_PAPR_ERR_INJ_MASK_CFG_LSH PPC_BITLSHIFT(11) +#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(14,40) /* 8M aligned */ +#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(40) #define PHB_ETU_ERR_SUMMARY 0x2c8 /* UTL registers */ |