ATTN: Set up attention area to handle attention

At present CPU control area ntuple in SPIRA structure is NULL.
ATTN component in Service Processor side checks for this field and if its empty,
it logs hardcoded SRC (0xBB821410) and generates SYSDUMP. So we have 1 SRC for
all failure (assert call) from OPAL side. This makes difficult to debug the issue.

Service processor provides attention area interface (FIPS PHyp Attentions spec),
so that we can pass SRC and user data (error message) to service processor.
This will helps us identify different failures in OPAL.

This patch enables attention area and provides interface (update_sp_attn_area())
to add src and user data (error message) through assert macro.

Attention SRC format:
	1st byte - Opal src type
	2-4 bytes - Holds the address of the assert function call

Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

3 files changed, 150 insertions, 0 deletions

diff --git a/include/fsp-attn.h b/include/fsp-attn.h
new file mode 100644
index 0000000..0149b7c
--- /dev/null
+++ b/include/fsp-attn.h
@@ -0,0 +1,142 @@
+/* Copyright 2013-2014 IBM Corp.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+* implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+#ifndef __FSP_ATTN_H
+#define __FSP_ATTN_H
+
+/* Per spec attn area can go up to 0x400  bytes */
+#define ATTN_AREA_SZ		0x400
+
+extern struct sp_attn_area cpu_ctl_sp_attn_area1;
+extern struct sp_attn_area cpu_ctl_sp_attn_area2;
+
+struct spat_entry {
+	/* Virtual address */
+	__be64	vaddr;
+	/* Partition id */
+	__be16	id;
+	uint8_t reserved[6];
+} __packed;
+
+/* SP Address Table: Structure is not used as of today, defined to
+ * keep in sync with the spec */
+struct sp_addr_table {
+	/* Index of last valid spat entry */
+	__be32			idx;
+	/* Number of SPAT entries allocated = 31 for SP */
+	__be32			count;
+	uint8_t			reserved1[8];
+	/* SPAT entries */
+	struct spat_entry	spat_entry[31];
+} __packed;
+
+/* SP Attention Areas */
+struct sp_attn_area {
+	/* Processor Number */
+	uint8_t		processor;
+	/* Attention command */
+	uint8_t		attn_cmd;
+	__be16		data_len;
+	uint8_t		data[];
+} __packed __align(ATTN_AREA_SZ);
+
+#define	SRC_WORD_COUNT	8
+#define SRC_LEN		32
+/* Max limit of user data size is 940 (due to attention area size) */
+#define TI_MSG_LEN	940
+/* Terminate Immediate Attention */
+struct ti_attn {
+	/* Command valid */
+	uint8_t		cmd_valid;
+	/* Attention command */
+	uint8_t		attn_cmd;
+	__be16		data_len;
+	/* Controls dump actions */
+	uint8_t		dump_ctrl;
+	uint8_t		reserved1;
+	/* Hardware dump type */
+	__be16		dump_type;
+	/* SRC format */
+	uint8_t		src_fmt;
+	/* SRC flags */
+	uint8_t		src_flags;
+	/* Number of ASCII words */
+	uint8_t		ascii_cnt;
+	/* Number of HEX words */
+	uint8_t		hex_cnt;
+	__be16		reserved2;
+	/* SRC length */
+	__be16		src_len;
+	__be32		src_word[SRC_WORD_COUNT];
+	/* ASCII data */
+	char		src[SRC_LEN];
+	uint32_t	msg_len;
+	/* User data: Simple error message */
+	char		msg[TI_MSG_LEN];
+} __packed __align(ATTN_AREA_SZ);
+
+/* Hypervisor Service Routine Data area: Structure is not used as of today,
+ * defined to keep in sync with the spec */
+struct hsr_data_area {
+	/* MS Address Compare Address */
+	__be64		ms_cmp_addr;
+	/* MS Address Compare Op (set/reset) */
+	__be16		ms_cmp_op;
+	/* MS Address Compare Length */
+	__be16		ms_cmp_len;
+	/* MS Address Compare Data */
+	__be32		ms_cmp_data;
+	/* MS Address Compare Service Routine */
+	__be64		ms_cmp_sr;
+	/* Pointer to MS Display / Alter HSR */
+	__be64		ms_display;
+	__be64		reserved1;
+	/* MS Dump HSR */
+	__be64		ms_dump_hsr;
+	/* Pointer to Real Address Validation HSR */
+	__be64		hsr_raddr;
+	/* Effective Address Field */
+	__be64		eaddr;
+	/* Pointer to CPU Spin HSR */
+	__be64		hsr_cpu_spin;
+	/* Pointer to SP Glue HSR */
+	__be64		hsr_sp_glue;
+	uint8_t		reserved2[19];
+	/* Time Base Flags
+	 * bit 7 (0x01) = 0b1: hardware time base disabled
+	 * other bits reserved
+	 */
+	uint8_t		time_flags;
+	uint8_t		reserved3[12];
+	/* TDE Addr Parm */
+	__be64		tde_addr;
+	/* SDR1 Shared Processor HSR */
+	__be64		hsr_sdr1_proc;
+	__be64		partition_id;
+	uint8_t		reserved4[12];
+	/* Address Type for Compare
+	 * 1 = real address
+	 * 2 = effective address
+	 * 3 = virtual address
+	 */
+	__be16		ms_addr_type;
+	uint8_t		reserved5[10];
+	/* Cache Flush Service Routine Pointer */
+	__be64		cfsr;
+	uint8_t         reserved6[88];
+} __packed;
+
+#endif	/* __FSP_ATTN_H */
diff --git a/include/fsp.h b/include/fsp.h
index 9541a8b..8e02ade 100644
--- a/include/fsp.h
+++ b/include/fsp.h
@@ -719,6 +719,9 @@ extern void fsp_code_update_wait_vpd(bool is_boot);
 extern void fsp_dump_init(void);
 extern void fsp_fips_dump_notify(uint32_t dump_id, uint32_t dump_len);
 
+/* Attention Handler */
+extern void fsp_attn_init(void);
+
 /* MDST table */
 extern void fsp_mdst_table_init(void);
 
diff --git a/include/mem-map.h b/include/mem-map.h
index effd689..2d01ab6 100644
--- a/include/mem-map.h
+++ b/include/mem-map.h
@@ -46,6 +46,11 @@
  */
 #define MDST_TABLE_OFF		(SPIRA_OFF + 0x1000)
 
+/* Like MDST, we need fixed address for CPU control header.
+ * We leave a 2k gap for MDST. CPU_CTL table is of size ~4k
+ */
+#define CPU_CTL_OFF             (SPIRA_OFF + 0x1800)
+
 /* We keep a gap of 2M for skiboot text & bss for now. We will
  * then we have our heap which goes up to base + 14M (so 12M for
  * now, though we can certainly reduce that a lot).