PCI: Refactor error injection

The patch refactors the code we had for PCI error injection. It
doesn't change the logic:

   * Rename names of error types and functions according to the
     comments given by Michael Ellerman when reviewing the kernel
     counterpart.
   * Split The backend of error injection for PHB3 and P7IOC to
     multiple functions to improve code readability. Some logics
     are simplified without affecting their original functionality.
   * Misc cleanup like renaming variables and functions.

Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2 files changed, 30 insertions, 28 deletions

diff --git a/include/opal.h b/include/opal.h
index fb0cee4..acb2bb5 100644
--- a/include/opal.h
+++ b/include/opal.h
@@ -131,7 +131,7 @@
 #define OPAL_PCI_SET_PHB_CAPI_MODE		93
 #define OPAL_DUMP_INFO2				94
 #define OPAL_WRITE_OPPANEL_ASYNC		95
-#define OPAL_PCI_ERR_INJCT			96
+#define OPAL_PCI_ERR_INJECT			96
 #define OPAL_PCI_EEH_FREEZE_SET			97
 #define OPAL_HANDLE_HMI				98
 #define OPAL_CONFIG_CPU_IDLE_STATE		99
@@ -191,31 +191,33 @@ enum OpalPciErrorSeverity {
 	OPAL_EEH_SEV_INF	= 5
 };
 
-enum OpalErrinjctType {
-	OpalErrinjctTypeIoaBusError		= 0,
-	OpalErrinjctTypeIoaBusError64		= 1,
-
-	/* IoaBusError & IoaBusError64 */
-	OpalEjtIoaLoadMemAddr			= 0,
-	OpalEjtIoaLoadMemData			= 1,
-	OpalEjtIoaLoadIoAddr			= 2,
-	OpalEjtIoaLoadIoData			= 3,
-	OpalEjtIoaLoadConfigAddr		= 4,
-	OpalEjtIoaLoadConfigData		= 5,
-	OpalEjtIoaStoreMemAddr			= 6,
-	OpalEjtIoaStoreMemData			= 7,
-	OpalEjtIoaStoreIoAddr			= 8,
-	OpalEjtIoaStoreIoData			= 9,
-	OpalEjtIoaStoreConfigAddr		= 10,
-	OpalEjtIoaStoreConfigData		= 11,
-	OpalEjtIoaDmaReadMemAddr		= 12,
-	OpalEjtIoaDmaReadMemData		= 13,
-	OpalEjtIoaDmaReadMemMaster		= 14,
-	OpalEjtIoaDmaReadMemTarget		= 15,
-	OpalEjtIoaDmaWriteMemAddr		= 16,
-	OpalEjtIoaDmaWriteMemData		= 17,
-	OpalEjtIoaDmaWriteMemMaster		= 18,
-	OpalEjtIoaDmaWriteMemTarget		= 19,
+enum OpalErrinjectType {
+	OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR	= 0,
+	OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64	= 1,
+};
+
+enum OpalErrinjectFunc {
+	/* IOA bus specific errors */
+	OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR	= 0,
+	OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA	= 1,
+	OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR	= 2,
+	OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA	= 3,
+	OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR	= 4,
+	OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA	= 5,
+	OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR	= 6,
+	OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA	= 7,
+	OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR	= 8,
+	OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA	= 9,
+	OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR	= 10,
+	OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA	= 11,
+	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR	= 12,
+	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA	= 13,
+	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER	= 14,
+	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET	= 15,
+	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR	= 16,
+	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA	= 17,
+	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER	= 18,
+	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET	= 19,
 };
 
 enum OpalShpcAction {
diff --git a/include/pci.h b/include/pci.h
index c15935c..9573961 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -257,8 +257,8 @@ struct phb_ops {
 				    uint64_t eeh_action_token);
 	int64_t (*eeh_freeze_set)(struct phb *phb, uint64_t pe_number,
 				  uint64_t eeh_action_token);
-	int64_t (*err_injct)(struct phb *phb, uint32_t pe_no, uint32_t type,
-			     uint32_t function, uint64_t addr, uint64_t mask);
+	int64_t (*err_inject)(struct phb *phb, uint32_t pe_no, uint32_t type,
+			      uint32_t func, uint64_t addr, uint64_t mask);
 	int64_t (*get_diag_data)(struct phb *phb, void *diag_buffer,
 				 uint64_t diag_buffer_len);
 	int64_t (*get_diag_data2)(struct phb *phb, void *diag_buffer,