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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-12-22 14:16:21 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-01-05 15:27:43 +1100 |
| commit | fdbb0580062c9cbf42cc5acc2222343c4a8b29f6 (patch) | |
| tree | 26865a773edeb2f7f6ba5018ecccfe8c5a1e0c1a /include/xive.h | |
| parent | eba2c3b1b4335f9de169d838bc24c2434bcd6977 (diff) | |
| download | skiboot-fdbb0580062c9cbf42cc5acc2222343c4a8b29f6.zip skiboot-fdbb0580062c9cbf42cc5acc2222343c4a8b29f6.tar.gz skiboot-fdbb0580062c9cbf42cc5acc2222343c4a8b29f6.tar.bz2 | |
xive: Implement cache watch and use it for EQs
We need to do cache coherent updates of the EQs when modifying
escalation interrupts. Use the cache watch facility for that.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/xive.h')
| -rw-r--r-- | include/xive.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/xive.h b/include/xive.h index ba48601..a6dc7be 100644 --- a/include/xive.h +++ b/include/xive.h @@ -107,6 +107,28 @@ #define PC_SCRUB_WANT_INVAL PPC_BIT(2) #define PC_SCRUB_BLOCK_ID PPC_BITMASK(27,31) #define PC_SCRUB_OFFSET PPC_BITMASK(45,63) +#define X_PC_VPC_CWATCH_SPEC 0x167 +#define PC_VPC_CWATCH_SPEC 0x738 +#define PC_VPC_CWATCH_CONFLICT PPC_BIT(0) +#define PC_VPC_CWATCH_FULL PPC_BIT(8) +#define PC_VPC_CWATCH_BLOCKID PPC_BITMASK(27,31) +#define PC_VPC_CWATCH_OFFSET PPC_BITMASK(45,63) +#define X_PC_VPC_CWATCH_DAT0 0x168 +#define PC_VPC_CWATCH_DAT0 0x740 +#define X_PC_VPC_CWATCH_DAT1 0x169 +#define PC_VPC_CWATCH_DAT1 0x748 +#define X_PC_VPC_CWATCH_DAT2 0x16a +#define PC_VPC_CWATCH_DAT2 0x750 +#define X_PC_VPC_CWATCH_DAT3 0x16b +#define PC_VPC_CWATCH_DAT3 0x758 +#define X_PC_VPC_CWATCH_DAT4 0x16c +#define PC_VPC_CWATCH_DAT4 0x760 +#define X_PC_VPC_CWATCH_DAT5 0x16d +#define PC_VPC_CWATCH_DAT5 0x768 +#define X_PC_VPC_CWATCH_DAT6 0x16e +#define PC_VPC_CWATCH_DAT6 0x770 +#define X_PC_VPC_CWATCH_DAT7 0x16f +#define PC_VPC_CWATCH_DAT7 0x778 /* VC0 register offsets */ #define X_VC_GLOBAL_CONFIG 0x200 @@ -144,6 +166,20 @@ #define VC_EQC_SCRUB_TRIG 0x910 #define X_VC_EQC_SCRUB_MASK 0x213 #define VC_EQC_SCRUB_MASK 0x918 +#define X_VC_EQC_CWATCH_SPEC 0x215 +#define VC_EQC_CWATCH_SPEC 0x928 +#define VC_EQC_CWATCH_CONFLICT PPC_BIT(0) +#define VC_EQC_CWATCH_FULL PPC_BIT(8) +#define VC_EQC_CWATCH_BLOCKID PPC_BITMASK(28,31) +#define VC_EQC_CWATCH_OFFSET PPC_BITMASK(40,63) +#define X_VC_EQC_CWATCH_DAT0 0x216 +#define VC_EQC_CWATCH_DAT0 0x930 +#define X_VC_EQC_CWATCH_DAT1 0x217 +#define VC_EQC_CWATCH_DAT1 0x938 +#define X_VC_EQC_CWATCH_DAT2 0x218 +#define VC_EQC_CWATCH_DAT2 0x940 +#define X_VC_EQC_CWATCH_DAT3 0x219 +#define VC_EQC_CWATCH_DAT3 0x948 #define X_VC_IVC_SCRUB_TRIG 0x222 #define VC_IVC_SCRUB_TRIG 0x990 #define X_VC_IVC_SCRUB_MASK 0x223 |