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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2016-12-22 14:16:16 +1100
committerStewart Smith <stewart@linux.vnet.ibm.com>2017-01-05 15:27:43 +1100
commit7147bd5f9405d503fd865e7dbc163c475bebd75b (patch)
treea4e373c1a5b921501d55e77a1773597af7aea9df /include/xive.h
parent48c6850c54de370d82e24e68bccb6bc5db3a32da (diff)
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xive: Add support for escalation interrupts
Escalation interrupts have their "IVE" entry buried inside of the EQ that shoots them which complicates matters. We want to expose them to the OS as normal interrupts, so we dedicate a bit in the interrupt number (outside the range supported by the OPAL emulation API) to differenciate them. The BlockID and Index in the interrupt number now refer to the source EQ. This is still missing proper cache management for them, which will come in a separate patch. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/xive.h')
-rw-r--r--include/xive.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/xive.h b/include/xive.h
index 065aa69..e35da6d 100644
--- a/include/xive.h
+++ b/include/xive.h
@@ -276,6 +276,9 @@
*
* One per interrupt source. Targets that interrupt to a given EQ
* and provides the corresponding logical interrupt number (EQ data)
+ *
+ * We also map this structure to the escalation descriptor inside
+ * an EQ, though in that case the valid and masked bits are not used.
*/
struct xive_ive {
/* Use a single 64-bit definition to make it easier to