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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-02-03 20:51:58 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-02-07 14:16:03 +1100 |
| commit | 7d252cdeb5f5f85d4a386859e0c87613162bcf31 (patch) | |
| tree | b0defc9d54750cdc509171eb2b5f3db3bc8bb77d /include/xive.h | |
| parent | dcffe14d4075ac9e8bfce6eb1c53401630a6582f (diff) | |
| download | skiboot-7d252cdeb5f5f85d4a386859e0c87613162bcf31.zip skiboot-7d252cdeb5f5f85d4a386859e0c87613162bcf31.tar.gz skiboot-7d252cdeb5f5f85d4a386859e0c87613162bcf31.tar.bz2 | |
xive/psi/lpc: Handle proper clearing of LPC SerIRQ latch on DD1
On DD1, the LPC SerIRQ are latched to 1 in HW but never back to 0,
we need an explicit clear after running the handler. (Not before
as they are level interrupts, they will be latched again if they
are still pending).
For now we do that in lpc_dispatch_ser_irqs() but that only works
for interrupts routed to OPAL.
In order to support routing LPC interrutps to Linux, we need a custom
EOI handler that does the clearing of the latch before we do the
EOI in the ESB.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/xive.h')
| -rw-r--r-- | include/xive.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/xive.h b/include/xive.h index e9a01c3..58c4da9 100644 --- a/include/xive.h +++ b/include/xive.h @@ -460,4 +460,8 @@ void xive_cpu_callin(struct cpu_thread *cpu); */ void *xive_get_trigger_port(uint32_t girq); +/* To be used by special EOI override in PSI */ +struct irq_source; +void __xive_source_eoi(struct irq_source *is, uint32_t isn); + #endif /* __XIVE_H__ */ |