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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-12-22 14:16:28 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-01-05 15:27:44 +1100 |
| commit | 2026df3ef2555215666c9b1aedad4998069f92de (patch) | |
| tree | ac0c41ef4271213c52943649d752281936e49704 /include/xive.h | |
| parent | 439b19e1588c657fdce5e3e14c5eaf4ff7060291 (diff) | |
| download | skiboot-2026df3ef2555215666c9b1aedad4998069f92de.zip skiboot-2026df3ef2555215666c9b1aedad4998069f92de.tar.gz skiboot-2026df3ef2555215666c9b1aedad4998069f92de.tar.bz2 | |
xive: Use an allocator for EQDs
This adds a bitmap allocator for EQDs. They are allocated in groups
of 8 naturally aligned. The VP structures associated with physical
CPUs now have all 8 EQDs available though only one is provisioned
and enabled.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/xive.h')
| -rw-r--r-- | include/xive.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/xive.h b/include/xive.h index e680427..f4e2696 100644 --- a/include/xive.h +++ b/include/xive.h @@ -234,6 +234,9 @@ * * Note: the address is naturally aligned, we don't use a PPC_BITMASK, * but just a mask to apply to the address before OR'ing it in. + * + * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the + * VSD and is only meant to be used in indirect mode ! */ #define VSD_MODE PPC_BITMASK(0,1) #define VSD_MODE_SHARED 1 @@ -243,6 +246,7 @@ #define VSD_MIGRATION_REG PPC_BITMASK(52,55) #define VSD_INDIRECT PPC_BIT(56) #define VSD_TSIZE PPC_BITMASK(59,63) +#define VSD_FIRMWARE PPC_BIT(2) /* Read warning above */ /* * TM registers are special, see below |