diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-06-24 14:17:06 -0500 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-06-26 14:28:58 +1000 |
| commit | c890a1ff25617a628d3a83d514c8dc4bcffac797 (patch) | |
| tree | 36dd66ab494b211f8d314ff7265707742ba91d65 /include/xive.h | |
| parent | 8019007766da1a09b0280d37ab9e5aa4df396e7f (diff) | |
| download | skiboot-c890a1ff25617a628d3a83d514c8dc4bcffac797.zip skiboot-c890a1ff25617a628d3a83d514c8dc4bcffac797.tar.gz skiboot-c890a1ff25617a628d3a83d514c8dc4bcffac797.tar.bz2 | |
xive: DD2.0 updates
Add support for StoreEOI, fix StoreEOI MMIO offset in ESB page,
and other cleanups
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/xive.h')
| -rw-r--r-- | include/xive.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/xive.h b/include/xive.h index d2ef1d9..bddb99c 100644 --- a/include/xive.h +++ b/include/xive.h @@ -74,6 +74,7 @@ #define X_PC_TCTXT_CFG 0x100 #define PC_TCTXT_CFG 0x400 #define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0) +#define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) #define PC_TCTXT_CHIPID PPC_BITMASK(12,15) @@ -102,6 +103,8 @@ #define X_PC_GLOBAL_CONFIG 0x110 #define PC_GLOBAL_CONFIG 0x480 #define PC_GCONF_INDIRECT PPC_BIT(32) +#define PC_GCONF_CHIPID_OVR PPC_BIT(40) +#define PC_GCONF_CHIPID PPC_BITMASK(44,47) #define X_PC_VSD_TABLE_ADDR 0x111 #define PC_VSD_TABLE_ADDR 0x488 #define X_PC_VSD_TABLE_DATA 0x112 @@ -225,6 +228,10 @@ #define VC_SBC_CACHE_SCRUB_TRIG 0xa10 #define VC_SBC_CACHE_SCRUB_MASK 0xa18 #define VC_SBC_CONFIG 0xa20 +#define X_VC_SBC_CONFIG 0x234 +#define VC_SBC_CONF_CPLX_CIST PPC_BIT(44) +#define VC_SBC_CONF_CIST_BOTH PPC_BIT(45) +#define VC_SBC_CONF_NO_UPD_PRF PPC_BIT(59) /* VC1 register offsets */ |