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| author | Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> | 2017-04-07 14:22:37 +0530 |
|---|---|---|
| committer | Michael Neuling <mikey@neuling.org> | 2017-04-12 16:49:36 +1000 |
| commit | 044fe827e02734451a1299166d1d020a7d57ff63 (patch) | |
| tree | 37923bb4af1848d88525bd66cf6beeaf05a04d57 /include/skiboot.h | |
| parent | 2fec26b312960aeee589d628b60cdd42ce83cca5 (diff) | |
| download | skiboot-044fe827e02734451a1299166d1d020a7d57ff63.zip skiboot-044fe827e02734451a1299166d1d020a7d57ff63.tar.gz skiboot-044fe827e02734451a1299166d1d020a7d57ff63.tar.bz2 | |
occ/irq: Fix SCOM address and irq reasons for P9 OCC
This patch fixes the SCOM address for OCC_MISC register which is used
for OCC interupts. In P9, OCC sends an interrupt to notify change in
the shared memory like throttle status. This patch handles this
interrupt reason.
Originally-from: Michael Neuling <mikey@neuling.org>
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Diffstat (limited to 'include/skiboot.h')
| -rw-r--r-- | include/skiboot.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/include/skiboot.h b/include/skiboot.h index 8bc767a..2b1f8a5 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -254,10 +254,13 @@ enum { extern void uart_set_console_policy(int policy); extern bool uart_enabled(void); -/* OCC interrupt */ -extern void occ_interrupt(uint32_t chip_id); +/* OCC interrupt for P8 */ +extern void occ_p8_interrupt(uint32_t chip_id); extern void occ_send_dummy_interrupt(void); +/* OCC interrupt for P9 */ +extern void occ_p9_interrupt(uint32_t chip_id); + /* OCC load support */ extern void occ_poke_load_queue(void); |