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| author | Stewart Smith <stewart@linux.ibm.com> | 2019-06-03 14:50:50 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-06-04 10:29:05 +1000 |
| commit | 16b7ae64103797b0ecab1dbb7c45df23b14810b9 (patch) | |
| tree | a3330ee950c4f93c9c7afe278cf1425f66366b95 /include/psi.h | |
| parent | 9cae036fafea468219892406a846639f2715854d (diff) | |
| download | skiboot-16b7ae64103797b0ecab1dbb7c45df23b14810b9.zip skiboot-16b7ae64103797b0ecab1dbb7c45df23b14810b9.tar.gz skiboot-16b7ae64103797b0ecab1dbb7c45df23b14810b9.tar.bz2 | |
Remove POWER7 and POWER7+ support
It's been a good long while since either OPAL POWER7 user touched a
machine, and even longer since they'd have been okay using an old
version rather than tracking master.
There's also been no testing of OPAL on POWER7 systems for an awfully
long time, so it's pretty safe to assume that it's very much bitrotted.
It also saves a whole 14kb of xz compressed payload space.
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Enthusiasticly-Acked-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include/psi.h')
| -rw-r--r-- | include/psi.h | 14 |
1 files changed, 1 insertions, 13 deletions
diff --git a/include/psi.h b/include/psi.h index 79555ec..ad56ce1 100644 --- a/include/psi.h +++ b/include/psi.h @@ -54,7 +54,7 @@ #define PSIHB_CR 0x20 #define PSIHB_CR_FSP_CMD_ENABLE PPC_BIT(0) #define PSIHB_CR_FSP_MMIO_ENABLE PPC_BIT(1) -#define PSIHB_CR_TCE_ENABLE PPC_BIT(2) /* P7 only */ +#define PSIHB_CR_TCE_ENABLE PPC_BIT(2) #define PSIHB_CR_FSP_IRQ_ENABLE PPC_BIT(3) #define PSIHB_CR_FSP_ERR_RSP_ENABLE PPC_BIT(4) #define PSIHB_CR_PSI_LINK_ENABLE PPC_BIT(5) @@ -81,9 +81,6 @@ /* PSI Status / Error Mask Register */ #define PSIHB_SEMR 0x28 -/* XIVR and BUID used for PSI interrupts on P7 */ -#define PSIHB_XIVR 0x30 - /* XIVR and BUID used for PSI interrupts on P8 */ #define PSIHB_XIVR_FSP 0x30 #define PSIHB_XIVR_OCC 0x60 @@ -123,13 +120,6 @@ /* * PSI Host Bridge Registers (XSCOM) */ -#define PSIHB_XSCOM_P7_HBBAR 0x9 -#define PSIHB_XSCOM_P7_HBBAR_EN PPC_BIT(28) -#define PSIHB_XSCOM_P7_HBCSR 0xd -#define PSIHB_XSCOM_P7_HBCSR_SET 0x11 -#define PSIHB_XSCOM_P7_HBCSR_CLR 0x12 -#define PSIHB_XSCOM_P7_HBSCR_FSP_IRQ PPC_BIT(13) - #define PSIHB_XSCOM_P8_BASE 0xa #define PSIHB_XSCOM_P8_HBBAR_EN PPC_BIT(63) #define PSIHB_XSCOM_P8_HBCSR 0xe @@ -166,8 +156,6 @@ /* * Layout of the PSI DMA address space * - * On P7, we instanciate a TCE table of 16K TCEs mapping 64M - * * On P8, we use a larger mapping of 256K TCEs which provides * us with a 1G window in order to fit the trace buffers * |