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| author | Nicholas Piggin <npiggin@gmail.com> | 2017-10-24 21:40:59 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-10-29 18:48:02 -0500 |
| commit | 90583f437bd6f82e47fac1616c4cab1e0ad84d6c (patch) | |
| tree | 68cad6b8157015df945e9428813ba6f7f847450a /include/processor.h | |
| parent | 7c154282947575d7478a3cda069095e4fbd7a632 (diff) | |
| download | skiboot-90583f437bd6f82e47fac1616c4cab1e0ad84d6c.zip skiboot-90583f437bd6f82e47fac1616c4cab1e0ad84d6c.tar.gz skiboot-90583f437bd6f82e47fac1616c4cab1e0ad84d6c.tar.bz2 | |
asm/head: initialize preferred DSCR value
POWER7/8 use DSCR=0. POWER9 preferred value has "stride-N" enabled.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/processor.h')
| -rw-r--r-- | include/processor.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/processor.h b/include/processor.h index 1f18762..77110d0 100644 --- a/include/processor.h +++ b/include/processor.h @@ -44,6 +44,7 @@ #define SPR_PIR_P7_MASK 0x03ff /* Mask of implemented bits */ /* SPR register definitions */ +#define SPR_DSCR 0x011 /* RW: Data stream control reg */ #define SPR_DSISR 0x012 /* RW: Data storage interrupt status reg */ #define SPR_DAR 0x013 /* RW: Data address reg */ #define SPR_DEC 0x016 /* RW: Decrement Register */ |