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| author | Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> | 2015-03-11 16:01:13 +0530 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-03-26 11:12:18 +1100 |
| commit | 9650f6b0a40dc21a6796c1ec66a7e5ddbb927947 (patch) | |
| tree | 3a57db7f5c3305a3e144137bd690bd703a2ee9f4 /include/processor.h | |
| parent | c426521c4b4286e49c15eaefc0a7b953effc25ec (diff) | |
| download | skiboot-9650f6b0a40dc21a6796c1ec66a7e5ddbb927947.zip skiboot-9650f6b0a40dc21a6796c1ec66a7e5ddbb927947.tar.gz skiboot-9650f6b0a40dc21a6796c1ec66a7e5ddbb927947.tar.bz2 | |
opal: Handle TFMR parity HMI event.
Handle TFMR parity errors reported through HMER[bit 5] and TFMR bit 60
i.e tx_tfmr_corrupt. For recovery, write '1' to TFMR bit 60 to clear it.
Once we clear this error, check for timebase machine state in TFMR [28:31]
and clear TB errors if timebase machine state is in error (9) state. Once
we reset the timebase machine state continue loading TOD into core TB.
To inject TFMR parity error issue:
$ putscom pu.ex 10013281 0001080000000000 -all
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/processor.h')
0 files changed, 0 insertions, 0 deletions