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| author | Russell Currey <ruscur@russell.cc> | 2017-06-09 16:06:04 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-06-15 13:37:37 +1000 |
| commit | 9953b4d15c4d47b11f9029b1b90f77537af1a715 (patch) | |
| tree | 85ba6f0ab3ed783eb62421612b0d9308abcebd79 /include/phb4-regs.h | |
| parent | cd48b15b132a5c7ea30ae3fa6f2144236b9ea88b (diff) | |
| download | skiboot-9953b4d15c4d47b11f9029b1b90f77537af1a715.zip skiboot-9953b4d15c4d47b11f9029b1b90f77537af1a715.tar.gz skiboot-9953b4d15c4d47b11f9029b1b90f77537af1a715.tar.bz2 | |
phb4: Mask link down errors during reset
During a hot reset the PCI link will drop, so we need to mask link down
events to prevent unnecessary errors.
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 92bee88..1ccef3a 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -288,6 +288,8 @@ #define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 #define PHB_PCIE_LANE_EQ_CNTL22 0x1B00 /* DD1 only */ #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */ +#define PHB_PCIE_TRACE_CTRL 0x1B20 +#define PHB_PCIE_MISC_STRAP 0x1B30 #define PHB_REGB_ERR_STATUS 0x1C00 #define PHB_REGB_ERR1_STATUS 0x1C08 |