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| author | Gavin Shan <gwshan@linux.vnet.ibm.com> | 2017-03-30 10:05:30 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-03-31 16:57:07 +1100 |
| commit | 2688ec9eeca1ce68b553220e57a9258b2f375192 (patch) | |
| tree | 074960955d2fc82c8e4eb4ed221038f1f5cb93c9 /include/phb3.h | |
| parent | 2e831a162653d53cb3e69cd98d75f0129752a643 (diff) | |
| download | skiboot-2688ec9eeca1ce68b553220e57a9258b2f375192.zip skiboot-2688ec9eeca1ce68b553220e57a9258b2f375192.tar.gz skiboot-2688ec9eeca1ce68b553220e57a9258b2f375192.tar.bz2 | |
hw/phb3: Adjust ECRC on root port dynamically
The issue was reported by Mark: the Samsung NVMe adapter is lost
when it's connected to PMC 8546 PCIe switch, until ECRC is disabled
on the root port. Actually, we found similar issue prevously when
Broadcom adapter is connected to same part of PCIe switch and it
was fixed by commit 60ce59ccd0e9 ("hw/phb3: Disable ECRC on Broadcom
adapter behind PMC switch"). Unfortunately, the commit doesn't fix
the Samsung NVMe adapter lost issue.
This fixes the issues by disable ECRC generation/check on root port
when PMC 8546 PCIe switch ports are found. This can be extended for
other PCIe switches or endpoints in future: Each PHB maintains the
count of PCI devices (PMC 8546 PCIe switch ports currently) which
require to disable ECRC on root port. The ECRC functionality is
enabled when first PMC 8546 switch port is probed and disabled when
last PMC 8546 switch port is destroyed (in PCI hot remove scenario).
Except PHB's reinitialization after complete reset, the ECRC on
root port is untouched.
Reported-by: Mark E Schreiter <markes@us.ibm.com>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Tested-by: Mark E Schreiter <markes@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb3.h')
| -rw-r--r-- | include/phb3.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/phb3.h b/include/phb3.h index cb36515..3f949fc 100644 --- a/include/phb3.h +++ b/include/phb3.h @@ -299,6 +299,7 @@ struct phb3 { int64_t aercap; /* cached AER ecap offset */ const __be64 *lane_eq; unsigned int max_link_speed; + uint32_t no_ecrc_devs; uint16_t rte_cache[RTT_TABLE_ENTRIES]; uint8_t peltv_cache[PELTV_TABLE_SIZE]; |