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| author | Gavin Shan <gwshan@linux.vnet.ibm.com> | 2015-10-01 11:10:41 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-10-07 16:59:09 +1100 |
| commit | 98fc754822051c22014a59126f5e7ab23dae23d7 (patch) | |
| tree | 036499fa2c674355d6022bf8917e1b6179cdaa95 /include/phb3.h | |
| parent | 3d340f2936f87517d8d449aba31a383fec3d2d17 (diff) | |
| download | skiboot-98fc754822051c22014a59126f5e7ab23dae23d7.zip skiboot-98fc754822051c22014a59126f5e7ab23dae23d7.tar.gz skiboot-98fc754822051c22014a59126f5e7ab23dae23d7.tar.bz2 | |
PHB3: Retry fundamental reset
When issuing fundamental reset on below IPR adapter that seats
behind root complex, there is 50% possibility that the link
fails to come up after the reset. In that case, the adapter's
config space is blocked and it's not usable.
host# lspci -ns 0004:01:00.0
0004:01:00.0 0104: 1014:034a (rev 01)
host# lspci -s 0004:01:00.0
0004:01:00.0 RAID bus controller: IBM PCI-E IPR SAS Adapter
(ASIC) (rev 01)
This introduces another PHB3 state (PHB3_STATE_FRESET_START)
allowing to redo fundamental reset if the link doesn't come up
in time at the first attempt, to improve the robustness of PHB's
fundamental reset. If the link comes up after the first reset,
the 2nd reset won't be issued at all.
Reported-by: Paul Nguyen <nguyenp@us.ibm.com>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb3.h')
| -rw-r--r-- | include/phb3.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/phb3.h b/include/phb3.h index 3accd9e..b2aae15 100644 --- a/include/phb3.h +++ b/include/phb3.h @@ -212,6 +212,7 @@ enum phb3_state { PHB3_STATE_HRESET_DELAY2, /* Fundamental reset */ + PHB3_STATE_FRESET_START, PHB3_STATE_FRESET_ASSERT_DELAY, PHB3_STATE_FRESET_DEASSERT_DELAY, @@ -291,6 +292,7 @@ struct phb3 { bool skip_perst; /* Skip first perst */ bool has_link; enum phb3_state state; + enum phb3_state retry_state; uint64_t delay_tgt_tb; uint64_t retries; int64_t ecap; /* cached PCI-E cap offset */ |