diff options
| author | Dan Streetman <ddstreet@ieee.org> | 2015-02-17 15:38:51 -0500 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-02-19 12:20:28 +1100 |
| commit | 7f91d66a0a3b0de9e6c729f031ee9adf9cea744b (patch) | |
| tree | a437651457118988abfd0def903dad75df94c149 /include/phb3-regs.h | |
| parent | 4a88a1452fe0e7f7d17d20aaf9b451969fb8c465 (diff) | |
| download | skiboot-7f91d66a0a3b0de9e6c729f031ee9adf9cea744b.zip skiboot-7f91d66a0a3b0de9e6c729f031ee9adf9cea744b.tar.gz skiboot-7f91d66a0a3b0de9e6c729f031ee9adf9cea744b.tar.bz2 | |
Change user-defined _MASK/_LSH to just mask
The last patch changed the SETFIELD() and GETFIELD() macros to automatically
calculate the shift of a given mask, so manually specifying the shift is no
longer needed. Additionally, any masks should have the _MASK suffix removed
since the GETFIELD() and SETFIELD() operations expected to be passed the
mask name without the _MASK suffix (and so either the mask name or the
get/setfield call needs to have its mask name changed).
Change all _MASK masks to remove the _MASK suffix, except for any places
that leaving _MASK makes sense (e.g. already an existing define without
_MASK suffix).
Remove all _LSH defines, as they are no longer needed.
Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb3-regs.h')
| -rw-r--r-- | include/phb3-regs.h | 156 |
1 files changed, 52 insertions, 104 deletions
diff --git a/include/phb3-regs.h b/include/phb3-regs.h index 686a113..144c344 100644 --- a/include/phb3-regs.h +++ b/include/phb3-regs.h @@ -24,8 +24,7 @@ /* PHB Fundamental register set A */ #define PHB_LSI_SOURCE_ID 0x100 -#define PHB_LSI_SRC_ID_MASK PPC_BITMASK(5,12) -#define PHB_LSI_SRC_ID_LSH PPC_BITLSHIFT(12) +#define PHB_LSI_SRC_ID PPC_BITMASK(5,12) #define PHB_DMA_CHAN_STATUS 0x110 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27) #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28) @@ -36,33 +35,24 @@ #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29) #define PHB_DMA_MSI_NODE_ID 0x128 #define PHB_DMAMSI_NID_FIXED PPC_BIT(0) -#define PHB_DMAMSI_NID_MASK PPC_BITMASK(24,31) -#define PHB_DMAMSI_NID_LSH PPC_BITLSHIFT(31) +#define PHB_DMAMSI_NID PPC_BITMASK(24,31) #define PHB_CONFIG_DATA 0x130 #define PHB_LOCK0 0x138 #define PHB_CONFIG_ADDRESS 0x140 #define PHB_CA_ENABLE PPC_BIT(0) -#define PHB_CA_BUS_MASK PPC_BITMASK(4,11) -#define PHB_CA_BUS_LSH PPC_BITLSHIFT(11) -#define PHB_CA_DEV_MASK PPC_BITMASK(12,16) -#define PHB_CA_DEV_LSH PPC_BITLSHIFT(16) -#define PHB_CA_FUNC_MASK PPC_BITMASK(17,19) -#define PHB_CA_FUNC_LSH PPC_BITLSHIFT(19) -#define PHB_CA_REG_MASK PPC_BITMASK(20,31) -#define PHB_CA_REG_LSH PPC_BITLSHIFT(31) -#define PHB_CA_PE_MASK PPC_BITMASK(40,47) -#define PHB_CA_PE_LSH PPC_BITLSHIFT(47) +#define PHB_CA_BUS PPC_BITMASK(4,11) +#define PHB_CA_DEV PPC_BITMASK(12,16) +#define PHB_CA_FUNC PPC_BITMASK(17,19) +#define PHB_CA_REG PPC_BITMASK(20,31) +#define PHB_CA_PE PPC_BITMASK(40,47) #define PHB_LOCK1 0x148 #define PHB_IVT_BAR 0x150 #define PHB_IVT_BAR_ENABLE PPC_BIT(0) -#define PHB_IVT_BASE_ADDRESS_MASK PPC_BITMASK(14,48) -#define PHB_IVT_BASE_ADDRESS_LSH PPC_BITLSHIFT(48) -#define PHB_IVT_LENGTH_MASK PPC_BITMASK(52,63) -#define PHB_IVT_LENGTH_ADDRESS_LSH PPC_BITLSHIFT(63) +#define PHB_IVT_BASE_ADDRESS PPC_BITMASK(14,48) +#define PHB_IVT_LENGTH PPC_BITMASK(52,63) #define PHB_RBA_BAR 0x158 #define PHB_RBA_BAR_ENABLE PPC_BIT(0) -#define PHB_RBA_BASE_ADDRESS_MASK PPC_BITMASK(14,55) -#define PHB_RBA_BASE_ADDRESS_LSH PPC_BITLSHIFT(55) +#define PHB_RBA_BASE_ADDRESS PPC_BITMASK(14,55) #define PHB_PHB3_CONFIG 0x160 #define PHB_PHB3C_64B_TCE_EN PPC_BIT(2) #define PHB_PHB3C_32BIT_MSI_EN PPC_BIT(8) @@ -70,40 +60,33 @@ #define PHB_PHB3C_M32_EN PPC_BIT(16) #define PHB_RTT_BAR 0x168 #define PHB_RTT_BAR_ENABLE PPC_BIT(0) -#define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(14,46) -#define PHB_RTT_BASE_ADDRESS_LSH PPC_BITLSHIFT(46) +#define PHB_RTT_BASE_ADDRESS PPC_BITMASK(14,46) #define PHB_PELTV_BAR 0x188 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0) -#define PHB_PELTV_BASE_ADDRESS_MASK PPC_BITMASK(14,50) -#define PHB_PELTV_BASE_ADDRESS_LSH PPC_BITLSHIFT(50) +#define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(14,50) #define PHB_M32_BASE_ADDR 0x190 #define PHB_M32_BASE_MASK 0x198 #define PHB_M32_START_ADDR 0x1a0 #define PHB_PEST_BAR 0x1a8 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) -#define PHB_PEST_BASE_ADDRESS_MASK PPC_BITMASK(14,51) -#define PHB_PEST_BASE_ADDRESS_LSH PPC_BITLSHIFT(51) +#define PHB_PEST_BASE_ADDRESS PPC_BITMASK(14,51) #define PHB_M64_UPPER_BITS 0x1f0 #define PHB_INTREP_TIMER 0x1f8 #define PHB_DMARD_SYNC 0x200 #define PHB_RTC_INVALIDATE 0x208 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) -#define PHB_RTC_INVALIDATE_RID_MASK PPC_BITMASK(16,31) -#define PHB_RTC_INVALIDATE_RID_LSH PPC_BITLSHIFT(31) +#define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16,31) #define PHB_TCE_KILL 0x210 #define PHB_TCE_KILL_ALL PPC_BIT(0) #define PHB_TCE_SPEC_CTL 0x218 #define PHB_IODA_ADDR 0x220 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) -#define PHB_IODA_AD_TSEL_MASK PPC_BITMASK(11,15) -#define PHB_IODA_AD_TSEL_LSH PPC_BITLSHIFT(15) -#define PHB_IODA_AD_TADR_MASK PPC_BITMASK(55,63) -#define PHB_IODA_AD_TADR_LSH PPC_BITLSHIFT(63) +#define PHB_IODA_AD_TSEL PPC_BITMASK(11,15) +#define PHB_IODA_AD_TADR PPC_BITMASK(55,63) #define PHB_IODA_DATA0 0x228 #define PHB_FFI_REQUEST 0x238 #define PHB_FFI_LOCK_CLEAR PPC_BIT(3) -#define PHB_FFI_REQUEST_ISN_MASK PPC_BITMASK(49,59) -#define PHB_FFI_REQUEST_ISN_LSH PPC_BITLSHIFT(59) +#define PHB_FFI_REQUEST_ISN PPC_BITMASK(49,59) #define PHB_FFI_LOCK 0x240 #define PHB_XIVE_UPDATE 0x248 /* Broken in DD1 */ #define PHB_PHB3_GEN_CAP 0x250 @@ -112,8 +95,7 @@ #define PHB_PHB3_EEH_CAP 0x268 #define PHB_IVC_INVALIDATE 0x2a0 #define PHB_IVC_INVALIDATE_ALL PPC_BIT(0) -#define PHB_IVC_INVALIDATE_SID_MASK PPC_BITMASK(16,31) -#define PHB_IVC_INVALIDATE_SID_LSH PPC_BITLSHIFT(31) +#define PHB_IVC_INVALIDATE_SID PPC_BITMASK(16,31) #define PHB_IVC_UPDATE 0x2a8 #define PHB_IVC_UPDATE_ENABLE_P PPC_BIT(0) #define PHB_IVC_UPDATE_ENABLE_Q PPC_BIT(1) @@ -121,20 +103,13 @@ #define PHB_IVC_UPDATE_ENABLE_PRI PPC_BIT(3) #define PHB_IVC_UPDATE_ENABLE_GEN PPC_BIT(4) #define PHB_IVC_UPDATE_ENABLE_CON PPC_BIT(5) -#define PHB_IVC_UPDATE_GEN_MATCH_MASK PPC_BITMASK(6, 7) -#define PHB_IVC_UPDATE_GEN_MATCH_LSH PPC_BITLSHIFT(7) -#define PHB_IVC_UPDATE_SERVER_MASK PPC_BITMASK(8, 23) -#define PHB_IVC_UPDATE_SERVER_LSH PPC_BITLSHIFT(23) -#define PHB_IVC_UPDATE_PRI_MASK PPC_BITMASK(24, 31) -#define PHB_IVC_UPDATE_PRI_LSH PPC_BITLSHIFT(31) -#define PHB_IVC_UPDATE_GEN_MASK PPC_BITMASK(32,33) -#define PHB_IVC_UPDATE_GEN_LSH PPC_BITLSHIFT(33) -#define PHB_IVC_UPDATE_P_MASK PPC_BITMASK(34,34) -#define PHB_IVC_UPDATE_P_LSH PPC_BITLSHIFT(34) -#define PHB_IVC_UPDATE_Q_MASK PPC_BITMASK(35,35) -#define PHB_IVC_UPDATE_Q_LSH PPC_BITLSHIFT(35) -#define PHB_IVC_UPDATE_SID_MASK PPC_BITMASK(48,63) -#define PHB_IVC_UPDATE_SID_LSH PPC_BITLSHIFT(63) +#define PHB_IVC_UPDATE_GEN_MATCH PPC_BITMASK(6, 7) +#define PHB_IVC_UPDATE_SERVER PPC_BITMASK(8, 23) +#define PHB_IVC_UPDATE_PRI PPC_BITMASK(24, 31) +#define PHB_IVC_UPDATE_GEN PPC_BITMASK(32,33) +#define PHB_IVC_UPDATE_P PPC_BITMASK(34,34) +#define PHB_IVC_UPDATE_Q PPC_BITMASK(35,35) +#define PHB_IVC_UPDATE_SID PPC_BITMASK(48,63) #define PHB_PAPR_ERR_INJ_CTL 0x2b0 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) @@ -144,13 +119,10 @@ #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 -#define PHB_PAPR_ERR_INJ_ADDR_MMIO_MASK PPC_BITMASK(16,63) -#define PHB_PAPR_ERR_INJ_ADDR_MMIO_LSH PPC_BITLSHIFT(63) +#define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16,63) #define PHB_PAPR_ERR_INJ_MASK 0x2c0 -#define PHB_PAPR_ERR_INJ_MASK_CFG_MASK PPC_BITMASK(4,11) -#define PHB_PAPR_ERR_INJ_MASK_CFG_LSH PPC_BITLSHIFT(11) -#define PHB_PAPR_ERR_INJ_MASK_MMIO_MASK PPC_BITMASK(16,63) -#define PHB_PAPR_ERR_INJ_MASK_MMIO_LSH PPC_BITLSHIFT(63) +#define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4,11) +#define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,63) #define PHB_ETU_ERR_SUMMARY 0x2c8 /* UTL registers */ @@ -340,39 +312,27 @@ #define IODA2_TBL_PEEV 20 /* LXIVT */ -#define IODA2_LXIVT_SERVER_MASK PPC_BITMASK(8,23) -#define IODA2_LXIVT_SERVER_LSH PPC_BITLSHIFT(23) -#define IODA2_LXIVT_PRIORITY_MASK PPC_BITMASK(24,31) -#define IODA2_LXIVT_PRIORITY_LSH PPC_BITLSHIFT(31) -#define IODA2_LXIVT_NODE_ID_MASK PPC_BITMASK(56,63) -#define IODA2_LXIVT_NODE_ID_LSH PPC_BITLSHIFT(63) +#define IODA2_LXIVT_SERVER PPC_BITMASK(8,23) +#define IODA2_LXIVT_PRIORITY PPC_BITMASK(24,31) +#define IODA2_LXIVT_NODE_ID PPC_BITMASK(56,63) /* IVT */ -#define IODA2_IVT_SERVER_MASK PPC_BITMASK(0,23) -#define IODA2_IVT_SERVER_LSH PPC_BITLSHIFT(23) -#define IODA2_IVT_PRIORITY_MASK PPC_BITMASK(24,31) -#define IODA2_IVT_PRIORITY_LSH PPC_BITLSHIFT(31) -#define IODA2_IVT_P_MASK PPC_BITMASK(39,39) -#define IODA2_IVT_P_LSH PPC_BITLSHIFT(39) -#define IODA2_IVT_Q_MASK PPC_BITMASK(47,47) -#define IODA2_IVT_Q_LSH PPC_BITLSHIFT(47) -#define IODA2_IVT_PE_MASK PPC_BITMASK(48,63) -#define IODA2_IVT_PE_LSH PPC_BITLSHIFT(63) +#define IODA2_IVT_SERVER PPC_BITMASK(0,23) +#define IODA2_IVT_PRIORITY PPC_BITMASK(24,31) +#define IODA2_IVT_P PPC_BITMASK(39,39) +#define IODA2_IVT_Q PPC_BITMASK(47,47) +#define IODA2_IVT_PE PPC_BITMASK(48,63) /* TVT */ -#define IODA2_TVT_TABLE_ADDR_MASK PPC_BITMASK(0,47) -#define IODA2_TVT_TABLE_ADDR_LSH PPC_BITLSHIFT(47) -#define IODA2_TVT_NUM_LEVELS_MASK PPC_BITMASK(48,50) -#define IODA2_TVT_NUM_LEVELS_LSH PPC_BITLSHIFT(50) +#define IODA2_TVT_TABLE_ADDR PPC_BITMASK(0,47) +#define IODA2_TVT_NUM_LEVELS PPC_BITMASK(48,50) #define IODA2_TVE_1_LEVEL 0 #define IODA2_TVE_2_LEVELS 1 #define IODA2_TVE_3_LEVELS 2 #define IODA2_TVE_4_LEVELS 3 #define IODA2_TVE_5_LEVELS 4 -#define IODA2_TVT_TCE_TABLE_SIZE_MASK PPC_BITMASK(51,55) -#define IODA2_TVT_TCE_TABLE_SIZE_LSH PPC_BITLSHIFT(55) -#define IODA2_TVT_IO_PSIZE_MASK PPC_BITMASK(59,63) -#define IODA2_TVT_IO_PSIZE_LSH PPC_BITLSHIFT(63) +#define IODA2_TVT_TCE_TABLE_SIZE PPC_BITMASK(51,55) +#define IODA2_TVT_IO_PSIZE PPC_BITMASK(59,63) /* PESTA */ #define IODA2_PESTA_MMIO_FROZEN PPC_BIT(0) @@ -381,24 +341,17 @@ #define IODA2_PESTB_DMA_STOPPED PPC_BIT(0) /* M32DT */ -#define IODA2_M32DT_PE_MASK PPC_BITMASK(8,15) -#define IODA2_M32DT_PE_LSH PPC_BITLSHIFT(15) +#define IODA2_M32DT_PE PPC_BITMASK(8,15) /* M64BT */ #define IODA2_M64BT_ENABLE PPC_BIT(0) #define IODA2_M64BT_SINGLE_PE PPC_BIT(1) -#define IODA2_M64BT_BASE_MASK PPC_BITMASK(2,31) -#define IODA2_M64BT_BASE_LSH PPC_BITLSHIFT(31) -#define IODA2_M64BT_MASK_MASK PPC_BITMASK(34,63) -#define IODA2_M64BT_MASK_LSH PPC_BITLSHIFT(63) -#define IODA2_M64BT_SINGLE_BASE_MASK PPC_BITMASK(2,26) -#define IODA2_M64BT_SINGLE_BASE_LSH PPC_BITLSHIFT(26) -#define IODA2_M64BT_PE_HI_MASK PPC_BITMASK(27,31) -#define IODA2_M64BT_PE_HI_LSH PPC_BITLSHIFT(31) -#define IODA2_M64BT_SINGLE_MASK_MASK PPC_BITMASK(34,58) -#define IODA2_M64BT_SINGLE_MASK_LSH PPC_BITLSHIFT(58) -#define IODA2_M64BT_PE_LOW_MASK PPC_BITMASK(59,63) -#define IODA2_M64BT_PE_LOW_LSH PPC_BITLSHIFT(63) +#define IODA2_M64BT_BASE PPC_BITMASK(2,31) +#define IODA2_M64BT_MASK PPC_BITMASK(34,63) +#define IODA2_M64BT_SINGLE_BASE PPC_BITMASK(2,26) +#define IODA2_M64BT_PE_HI PPC_BITMASK(27,31) +#define IODA2_M64BT_SINGLE_MASK PPC_BITMASK(34,58) +#define IODA2_M64BT_PE_LOW PPC_BITMASK(59,63) /* * IODA2 in-memory tables @@ -412,8 +365,7 @@ #define IODA2_PEST0_MMIO_CAUSE PPC_BIT(2) #define IODA2_PEST0_CFG_READ PPC_BIT(3) #define IODA2_PEST0_CFG_WRITE PPC_BIT(4) -#define IODA2_PEST0_TTYPE_MASK PPC_BITMASK(5,7) -#define IODA2_PEST0_TTYPE_LSH PPC_BITLSHIFT(7) +#define IODA2_PEST0_TTYPE PPC_BITMASK(5,7) #define PEST_TTYPE_DMA_WRITE 0 #define PEST_TTYPE_MSI 1 #define PEST_TTYPE_DMA_READ 2 @@ -435,15 +387,11 @@ #define IODA2_PEST0_TCE_ACCESS_FAULT PPC_BIT(19) #define IODA2_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20) #define IODA2_PEST0_AIB_SIZE_INVALID PPC_BIT(21) -#define IODA2_PEST0_LEM_BIT_MASK PPC_BITMASK(26,31) -#define IODA2_PEST0_LEM_BIT_LSH PPC_BITLSHIFT(31) -#define IODA2_PEST0_RID_MASK PPC_BITMASK(32,47) -#define IODA2_PEST0_RID_LSH PPC_BITLSHIFT(47) -#define IODA2_PEST0_MSI_DATA_MASK PPC_BITMASK(48,63) -#define IODA2_PEST0_MSI_DATA_LSH PPC_BITLSHIFT(63) +#define IODA2_PEST0_LEM_BIT PPC_BITMASK(26,31) +#define IODA2_PEST0_RID PPC_BITMASK(32,47) +#define IODA2_PEST0_MSI_DATA PPC_BITMASK(48,63) -#define IODA2_PEST1_FAIL_ADDR_MASK PPC_BITMASK(3,63) -#define IODA2_PEST1_FAIL_ADDR_LSH PPC_BITLSHIFT(63) +#define IODA2_PEST1_FAIL_ADDR PPC_BITMASK(3,63) #endif /* __PHB3_REGS_H */ |