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| author | Alistair Popple <alistair@popple.id.au> | 2017-03-24 12:22:23 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-03-30 19:37:48 +1100 |
| commit | d8c880ecc2c8308395e51e28b12fb19a826dc0f6 (patch) | |
| tree | 10f6627ea89d7200c1201d483e41e3c6d9f7313b /include/pci.h | |
| parent | 98509ad54e14fe524ef0833a1bde35547ba2785f (diff) | |
| download | skiboot-d8c880ecc2c8308395e51e28b12fb19a826dc0f6.zip skiboot-d8c880ecc2c8308395e51e28b12fb19a826dc0f6.tar.gz skiboot-d8c880ecc2c8308395e51e28b12fb19a826dc0f6.tar.bz2 | |
Introduce NPU2 support
NVLink2 is a new feature introduced on POWER9 systems. It is an
evolution of of the NVLink1 feature included in POWER8+ systems but
adds several new features including support for GPU address
translation using the Nest MMU and cache coherence.
Similar to NVLink1 the functionality is exposed to the OS as a series
of virtual PCIe devices. However the actual hardware interfaces are
significantly different which limits the amount of common code that
can be shared between implementations in the firmware.
This patch adds basic hardware initialisation and exposure of the
virtual NVLink2 PCIe devices to the running OS.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/pci.h')
| -rw-r--r-- | include/pci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/pci.h b/include/pci.h index 44bedf6..732c1a3 100644 --- a/include/pci.h +++ b/include/pci.h @@ -328,6 +328,7 @@ enum phb_type { phb_type_pcie_v2, phb_type_pcie_v3, phb_type_pcie_v4, + phb_type_npu_v2, }; struct phb { |