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authorGavin Shan <gwshan@linux.vnet.ibm.com>2016-08-11 12:12:37 +1000
committerStewart Smith <stewart@linux.vnet.ibm.com>2016-09-02 15:27:39 +1000
commit85daa7f00c5001593f28eb0e975b94921f3cd023 (patch)
treea3ff8b15610c021c9851a1e0349e81bdd4e036c1 /include/pci-virt.h
parentb9801047a12c27d1d205ba5c250a9c399a9f8fd1 (diff)
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core/pci: Support virtual device
The NVLinks (v1 and v2 to be supported in future) are exposed to Linux kernel by emulated PCI devices (aka PCI virtual devices). Currently, the implementation is covered by NVLink driver (npu.c), meaning npu2.c will have similar implementation though it will be totally duplicated with that in npu.c. This supports PCI virtual device in the generic layer so that it can be shared by all NVLink drivers. The design is highlighted as: * There are 3 config spaces for every PCI virtual device, corresponds to the cached config space, readonly space, write-1-clear space. * Reuse PCI config register filter mechanism to allow NVLink driver to emulate the access to the designated config registers. The config values are fetched from or written to the cached config space when the config registers aren't covered by filter. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/pci-virt.h')
-rw-r--r--include/pci-virt.h85
1 files changed, 85 insertions, 0 deletions
diff --git a/include/pci-virt.h b/include/pci-virt.h
new file mode 100644
index 0000000..7c787cf
--- /dev/null
+++ b/include/pci-virt.h
@@ -0,0 +1,85 @@
+/* Copyright 2013-2016 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PCI_VIRT_H
+#define __PCI_VIRT_H
+
+#include <ccan/list/list.h>
+
+enum {
+ PCI_VIRT_CFG_NORMAL,
+ PCI_VIRT_CFG_RDONLY,
+ PCI_VIRT_CFG_W1CLR,
+ PCI_VIRT_CFG_MAX
+};
+
+struct pci_virt_device {
+ uint32_t bdfn;
+ uint32_t cfg_size;
+ uint8_t *config[PCI_VIRT_CFG_MAX];
+ struct list_head pcrf;
+ struct list_node node;
+ void *data;
+};
+
+extern void pci_virt_cfg_read_raw(struct pci_virt_device *pvd,
+ uint32_t space, uint32_t offset,
+ uint32_t size, uint32_t *data);
+extern void pci_virt_cfg_write_raw(struct pci_virt_device *pvd,
+ uint32_t space, uint32_t offset,
+ uint32_t size, uint32_t data);
+extern struct pci_cfg_reg_filter *pci_virt_add_filter(
+ struct pci_virt_device *pvd,
+ uint32_t start, uint32_t len,
+ uint32_t flags, pci_cfg_reg_func func,
+ void *data);
+extern int64_t pci_virt_cfg_read(struct phb *phb, uint32_t bdfn,
+ uint32_t offset, uint32_t size,
+ uint32_t *data);
+extern int64_t pci_virt_cfg_write(struct phb *phb, uint32_t bdfn,
+ uint32_t offset, uint32_t size,
+ uint32_t data);
+extern struct pci_virt_device *pci_virt_find_device(struct phb *phb,
+ uint32_t bdfn);
+extern struct pci_virt_device *pci_virt_add_device(struct phb *phb,
+ uint32_t bdfn,
+ uint32_t cfg_size,
+ void *data);
+
+/* Config space accessors */
+#define PCI_VIRT_CFG_NORMAL_RD(d, o, s, v) \
+ pci_virt_cfg_read_raw(d, PCI_VIRT_CFG_NORMAL, o, s, v)
+#define PCI_VIRT_CFG_NORMAL_WR(d, o, s, v) \
+ pci_virt_cfg_write_raw(d, PCI_VIRT_CFG_NORMAL, o, s, v)
+#define PCI_VIRT_CFG_RDONLY_RD(d, o, s, v) \
+ pci_virt_cfg_read_raw(d, PCI_VIRT_CFG_RDONLY, o, s, v)
+#define PCI_VIRT_CFG_RDONLY_WR(d, o, s, v) \
+ pci_virt_cfg_write_raw(d, PCI_VIRT_CFG_RDONLY, o, s, v)
+#define PCI_VIRT_CFG_W1CLR_RD(d, o, s, v) \
+ pci_virt_cfg_read_raw(d, PCI_VIRT_CFG_W1CLR, o, s, v)
+#define PCI_VIRT_CFG_W1CLR_WR(d, o, s, v) \
+ pci_virt_cfg_write_raw(d, PCI_VIRT_CFG_W1CLR, o, s, v)
+
+#define PCI_VIRT_CFG_INIT(d, o, s, v, r, w) \
+ do { \
+ PCI_VIRT_CFG_NORMAL_WR(d, o, s, v); \
+ PCI_VIRT_CFG_RDONLY_WR(d, o, s, r); \
+ PCI_VIRT_CFG_W1CLR_WR(d, o, s, w); \
+ } while (0)
+#define PCI_VIRT_CFG_INIT_RO(d, o, s, v) \
+ PCI_VIRT_CFG_INIT(d, o, s, v, 0xffffffff, 0)
+
+#endif /* __VIRT_PCI_H */