core/pci: Use PCI slot's power facality in pci_enable_bridge()

The current implmentation has incorrect assumptions: there is
always a PCI slot associated with root port and PCIe switch
downstream port and all of them are capable to change its
power state by register PCICAP_EXP_SLOTCTL. Firstly, there
might not a PCI slot associated with the root port or PCIe
switch downstream port. Secondly, the power isn't controlled
by standard config register (PCICAP_EXP_SLOTCTL). There are
I2C slave devices used to control the power states on Tuleta.

In order to use the PCI slot's methods to manage the power
states, this does:

  * Introduce PCI_SLOT_FLAG_ENFORCE, indicates the request operation
    is enforced to be applied.
  * pci_enable_bridge() is split into 3 functions: pci_bridge_power_on()
    to power it on; pci_enable_bridge() as a place holder and
    pci_bridge_wait_link() to wait the downstream link to come up.
  * In pci_bridge_power_on(), the PCI slot's specific power management
    methods are used if there is a PCI slot associated with the PCIe
    switch downstream port or root port.

Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/include/pci-slot.h b/include/pci-slot.h
index 03d966b..1d031ea 100644
--- a/include/pci-slot.h
+++ b/include/pci-slot.h
@@ -148,6 +148,7 @@ struct pci_slot {
 #define PCI_SLOT_FLAG_BOOTUP		0x1
 #define PCI_SLOT_FLAG_FORCE_POWERON	0x2
 #define PCI_SLOT_FLAG_BROKEN_PDC	0x4
+#define PCI_SLOT_FLAG_ENFORCE		0x8
 
 	struct phb		*phb;
 	struct pci_device	*pd;