phb4: Improve reset and link training timing

This improves PHB reset and link training timing. Justifications and
reasons are included in the patch.

Polling frequencies are decreased from 100ms to 10ms.

Added is a new state called PHB4_SLOT_LINK_STABLE which is now needed
since the link training can be so fast that we touch config space too
quickly (PCIe spec requires 1 second between PERST de-assert and
device config space reads). We use this new state to sanity check the
PHB and link before moving onto the PCI bus scan, where we no longer
recover from these error conditions.

Also added is simplified documentation of the PHB reset and training flow.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/include/pci-slot.h b/include/pci-slot.h
index 479bc08..5cc54f8 100644
--- a/include/pci-slot.h
+++ b/include/pci-slot.h
@@ -185,6 +185,7 @@ struct pci_slot {
 	uint64_t		delay_tgt_tb;
 	uint64_t		retries;
 	uint64_t		link_retries;
+	uint64_t		stable_retries;
 	struct pci_slot_ops	ops;
 	void			*data;
 };