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authorDan Streetman <ddstreet@ieee.org>2015-02-17 15:38:51 -0500
committerStewart Smith <stewart@linux.vnet.ibm.com>2015-02-19 12:20:28 +1100
commit7f91d66a0a3b0de9e6c729f031ee9adf9cea744b (patch)
treea437651457118988abfd0def903dad75df94c149 /include/pci-cfg.h
parent4a88a1452fe0e7f7d17d20aaf9b451969fb8c465 (diff)
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Change user-defined _MASK/_LSH to just mask
The last patch changed the SETFIELD() and GETFIELD() macros to automatically calculate the shift of a given mask, so manually specifying the shift is no longer needed. Additionally, any masks should have the _MASK suffix removed since the GETFIELD() and SETFIELD() operations expected to be passed the mask name without the _MASK suffix (and so either the mask name or the get/setfield call needs to have its mask name changed). Change all _MASK masks to remove the _MASK suffix, except for any places that leaving _MASK makes sense (e.g. already an existing define without _MASK suffix). Remove all _LSH defines, as they are no longer needed. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/pci-cfg.h')
-rw-r--r--include/pci-cfg.h116
1 files changed, 39 insertions, 77 deletions
diff --git a/include/pci-cfg.h b/include/pci-cfg.h
index 7c98f3f..c705d25 100644
--- a/include/pci-cfg.h
+++ b/include/pci-cfg.h
@@ -46,7 +46,7 @@
#define PCI_CFG_HDR_TYPE 0x000e
#define PCI_CFG_BIST 0x000f
#define PCI_CFG_BAR0 0x0010
-#define PCI_CFG_BAR_TYPE_MASK 0x00000001
+#define PCI_CFG_BAR_TYPE 0x00000001
#define PCI_CFG_BAR_TYPE_MEM 0x00000000
#define PCI_CFG_BAR_TYPE_IO 0x00000001
#define PCI_CFG_BAR_MEM64 0x00000004
@@ -117,10 +117,8 @@
#define PCI_CFG_CAP_ID_EXP 0x10
/* PCI Express capability fields */
#define PCICAP_EXP_CAPABILITY_REG 0x02
-#define PCICAP_EXP_CAP_VERSION_MASK 0x000f
-#define PCICAP_EXP_CAP_VERSION_LSH 0
-#define PCICAP_EXP_CAP_TYPE_MASK 0x00f0
-#define PCICAP_EXP_CAP_TYPE_LSH 4
+#define PCICAP_EXP_CAP_VERSION 0x000f
+#define PCICAP_EXP_CAP_TYPE 0x00f0
#define PCIE_TYPE_ENDPOINT 0x0
#define PCIE_TYPE_LEGACY 0x1
#define PCIE_TYPE_ROOT_PORT 0x4
@@ -131,27 +129,23 @@
#define PCIE_TYPE_RC_INTEGRATED 0x9
#define PCIE_TYPE_RC_EVT_COLL 0xa
#define PCICAP_EXP_CAP_SLOT 0x0100
-#define PCICAP_EXP_CAP_MSI_NUM_MASK 0x3e00
-#define PCICAP_EXP_CAP_MSI_NUM_LSH 9
+#define PCICAP_EXP_CAP_MSI_NUM 0x3e00
#define PCICAP_EXP_CAP_TCS_ROUTING 0x4000
#define PCICAP_EXP_DEVCAP 0x04
-#define PCICAP_EXP_DEVCAP_MPSS_MASK 0x00000007
-#define PCICAP_EXP_DEVCAP_MPSS_LSH 0
+#define PCICAP_EXP_DEVCAP_MPSS 0x00000007
#define PCIE_MPSS_128 0
#define PCIE_MPSS_256 1
#define PCIE_MPSS_512 2
#define PCIE_MPSS_1024 3
#define PCIE_MPSS_2048 4
#define PCIE_MPSS_4096 5
-#define PCICAP_EXP_DEVCAP_PHANT_MASK 0x00000018
-#define PCICAP_EXP_DEVCAP_PHANT_LSH 3
+#define PCICAP_EXP_DEVCAP_PHANT 0x00000018
#define PCIE_PHANTOM_NONE 0
#define PCIE_PHANTOM_1MSB 1
#define PCIE_PHANTOM_2MSB 2
#define PCIE_PHANTOM_3MSB 3
#define PCICAP_EXP_DEVCAP_EXTTAG 0x00000020
-#define PCICAP_EXP_DEVCAP_L0SL_MASK 0x000001c0
-#define PCICAP_EXP_DEVCAP_L0SL_LSH 6
+#define PCICAP_EXP_DEVCAP_L0SL 0x000001c0
#define PCIE_L0SL_MAX_64NS 0
#define PCIE_L0SL_MAX_128NS 1
#define PCIE_L0SL_MAX_256NS 2
@@ -160,8 +154,7 @@
#define PCIE_L0SL_MAX_2US 5
#define PCIE_L0SL_MAX_4US 6
#define PCIE_L0SL_MAX_NO_LIMIT 7
-#define PCICAP_EXP_DEVCAP_L1L_MASK 0x00000e00
-#define PCICAP_EXP_DEVCAP_L1L_LSH 9
+#define PCICAP_EXP_DEVCAP_L1L 0x00000e00
#define PCIE_L1L_MAX_1US 0
#define PCIE_L1L_MAX_2US 1
#define PCIE_L1L_MAX_4US 2
@@ -171,10 +164,8 @@
#define PCIE_L1L_MAX_64US 6
#define PCIE_L1L_MAX_NO_LIMIT 7
#define PCICAP_EXP_ROLE_BASED_ERR 0x00008000
-#define PCICAP_EXP_DEVCAP_PWRVAL_MASK 0x03fc0000
-#define PCICAP_EXP_DEVCAP_PWRVAL_LSH 18
-#define PCICAP_EXP_DEVCAP_PWRSCA_MASK 0x0c000000
-#define PCICAP_EXP_DEVCAP_PWRSCA_LSH 26
+#define PCICAP_EXP_DEVCAP_PWRVAL 0x03fc0000
+#define PCICAP_EXP_DEVCAP_PWRSCA 0x0c000000
#define PCIE_SLOT_PWR_SCALE_1x 0
#define PCIE_SLOT_PWR_SCALE_0d1x 1
#define PCIE_SLOT_PWR_SCALE_0d01x 2
@@ -186,8 +177,7 @@
#define PCICAP_EXP_DEVCTL_FE_REPORT 0x0004
#define PCICAP_EXP_DEVCTL_UR_REPORT 0x0008
#define PCICAP_EXP_DEVCTL_RELAX_ORD 0x0010
-#define PCICAP_EXP_DEVCTL_MPS_MASK 0x00e0
-#define PCICAP_EXP_DEVCTL_MPS_LSH 5
+#define PCICAP_EXP_DEVCTL_MPS 0x00e0
#define PCIE_MPS_128B 0
#define PCIE_MPS_256B 1
#define PCIE_MPS_512B 2
@@ -198,8 +188,7 @@
#define PCICAP_EXP_DEVCTL_PHANTOM 0x0200
#define PCICAP_EXP_DEVCTL_AUX_POW_PM 0x0400
#define PCICAP_EXP_DEVCTL_NO_SNOOP 0x0800
-#define PCICAP_EXP_DEVCTL_MRRS_MASK 0x7000
-#define PCICAP_EXP_DEVCTL_MRRS_LSH 12
+#define PCICAP_EXP_DEVCTL_MRRS 0x7000
#define PCIE_MRSS_128B 0
#define PCIE_MRSS_256B 1
#define PCIE_MRSS_512B 2
@@ -216,8 +205,7 @@
#define PCICAP_EXP_DEVSTAT_AUX_POW 0x0010
#define PCICAP_EXP_DEVSTAT_TPEND 0x0020
#define PCICAP_EXP_LCAP 0x0c
-#define PCICAP_EXP_LCAP_MAXSPD_MASK 0x0000000f
-#define PCICAP_EXP_LCAP_MAXSPD_LSH 0
+#define PCICAP_EXP_LCAP_MAXSPD 0x0000000f
#define PCIE_LSPEED_VECBIT_0 0x1
#define PCIE_LSPEED_VECBIT_1 0x2
#define PCIE_LSPEED_VECBIT_2 0x3
@@ -225,8 +213,7 @@
#define PCIE_LSPEED_VECBIT_4 0x5
#define PCIE_LSPEED_VECBIT_5 0x6
#define PCIE_LSPEED_VECBIT_6 0x7
-#define PCICAP_EXP_LCAP_MAXWDTH_MASK 0x000003f0
-#define PCICAP_EXP_LCAP_MAXWDTH_LSH 4
+#define PCICAP_EXP_LCAP_MAXWDTH 0x000003f0
#define PCIE_LWIDTH_1X 1
#define PCIE_LWIDTH_2X 2
#define PCIE_LWIDTH_4X 4
@@ -236,8 +223,7 @@
#define PCIE_LWIDTH_32X 32
#define PCICAP_EXP_LCAP_ASPM_L0S 0x00000400
#define PCICAP_EXP_LCAP_ASPM_L1 0x00000800
-#define PCICAP_EXP_LCAP_L0S_EXLT_MASK 0x00007000
-#define PCICAP_EXP_LCAP_L0S_EXLT_LSH 12
+#define PCICAP_EXP_LCAP_L0S_EXLT 0x00007000
#define PCIE_L0S_EXLT_LESS_64NS 0
#define PCIE_L0S_EXLT_64NS_128NS 1
#define PCIE_L0S_EXLT_128NS_256NS 2
@@ -246,8 +232,7 @@
#define PCIE_L0S_EXLT_1US_2US 5
#define PCIE_L0S_EXLT_2US_4US 6
#define PCIE_L0S_EXLT_MORE_4US 7
-#define PCICAP_EXP_LCAP_L1_EXLT_MASK 0x00038000
-#define PCICAP_EXP_LCAP_L1_EXLT_LSH 15
+#define PCICAP_EXP_LCAP_L1_EXLT 0x00038000
#define PCIE_L1_EXLT_LESS_1US 0
#define PCIE_L1_EXLT_1US_2US 1
#define PCIE_L1_EXLT_2US_4US 2
@@ -261,8 +246,7 @@
#define PCICAP_EXP_LCAP_DL_ACT_REP 0x00100000
#define PCICAP_EXP_LCAP_LNKBWDTH_NOTF 0x00200000
#define PCICAP_EXP_LCAP_ASPM_OPT_CMPL 0x00400000
-#define PCICAP_EXP_LCAP_PORTNUM_MASK 0xff000000
-#define PCICAP_EXP_LCAP_PORTNUM_LSH 24
+#define PCICAP_EXP_LCAP_PORTNUM 0xff000000
#define PCICAP_EXP_LCTL 0x10
#define PCICAP_EXP_LCTL_ASPM_L0S 0x0001
#define PCICAP_EXP_LCTL_ASPM_L1 0x0002
@@ -276,10 +260,8 @@
#define PCICAP_EXP_LCTL_LBWM_INT_EN 0x0400
#define PCICAP_EXP_LCTL_LAWD_INT_EN 0x0800
#define PCICAP_EXP_LSTAT 0x12
-#define PCICAP_EXP_LSTAT_SPEED_MASK 0x000f
-#define PCICAP_EXP_LSTAT_SPEED_LSH 0 /* use PCIE_LSPEED_* consts */
-#define PCICAP_EXP_LSTAT_WIDTH_MASK 0x03f0
-#define PCICAP_EXP_LSTAT_WIDTH_LSH 4 /* use PCIE_LWIDTH_* consts */
+#define PCICAP_EXP_LSTAT_SPEED 0x000f /* use PCIE_LSPEED_* consts */
+#define PCICAP_EXP_LSTAT_WIDTH 0x03f0 /* use PCIE_LWIDTH_* consts */
#define PCICAP_EXP_LSTAT_TRAINING 0x0800
#define PCICAP_EXP_LSTAT_SLOTCLKCFG 0x1000
#define PCICAP_EXP_LSTAT_DLLL_ACT 0x2000
@@ -293,14 +275,11 @@
#define PCICAP_EXP_SLOTCAP_PWRI 0x00000010
#define PCICAP_EXP_SLOTCAP_HPLUG_SURP 0x00000020
#define PCICAP_EXP_SLOTCAP_HPLUG_CAP 0x00000040
-#define PCICAP_EXP_SLOTCAP_SPLVA_MASK 0x00007f80
-#define PCICAP_EXP_SLOTCAP_SPLLVA_LSH 7
-#define PCICAP_EXP_SLOTCAP_SPLSC_MASK 0x00018000
-#define PCICAP_EXP_SLOTCAP_SPLSC_LSH 15
+#define PCICAP_EXP_SLOTCAP_SPLVA 0x00007f80
+#define PCICAP_EXP_SLOTCAP_SPLSC 0x00018000
#define PCICAP_EXP_SLOTCAP_EIP 0x00020000
#define PCICAP_EXP_SLOTCAP_NO_CMDCOMP 0x00040000
-#define PCICAP_EXP_SLOTCAP_PSLOT_MASK 0xfff80000
-#define PCICAP_EXP_SLOTCAP_PSLOT_LSH 19
+#define PCICAP_EXP_SLOTCAP_PSLOT 0xfff80000
#define PCICAP_EXP_SLOTCTL 0x18
#define PCICAP_EXP_SLOTCTL_ATTNB 0x0001
#define PCICAP_EXP_SLOTCTL_PFLT 0x0002
@@ -308,13 +287,11 @@
#define PCICAP_EXP_SLOTCTL_PDETECT 0x0008
#define PCICAP_EXP_SLOTCTL_CMDCOMPINT 0x0010
#define PCICAP_EXP_SLOTCTL_HPINT 0x0020
-#define PCICAP_EXP_SLOTCTL_ATTNI_MASK 0x00c0
-#define PCICAP_EXP_SLOTCTL_ATTNI_LSH 6
+#define PCICAP_EXP_SLOTCTL_ATTNI 0x00c0
#define PCIE_INDIC_ON 1
#define PCIE_INDIC_BLINK 2
#define PCIE_INDIC_OFF 3
-#define PCICAP_EXP_SLOTCTL_PWRI_MASK 0x0300
-#define PCICAP_EXP_SLOTCTL_PWRI_LSH 8 /* Use PCIE_INDIC_* consts */
+#define PCICAP_EXP_SLOTCTL_PWRI 0x0300 /* Use PCIE_INDIC_* consts */
#define PCICAP_EXP_SLOTCTL_PWRCTLR 0x0400
#define PCICAP_EXP_SLOTCTL_EIC 0x0800
#define PCICAP_EXP_SLOTCTL_DLLSTCHG 0x1000
@@ -337,13 +314,11 @@
#define PCICAP_EXP_RCAP 0x1e
#define PCICAP_EXP_RCAP_CRS_VISIBLE 0x0001
#define PCICAP_EXP_RSTAT 0x20
-#define PCICAP_EXP_RSTAT_PME_RID_MASK 0x0000ffff
-#define PCICAP_EXP_RSTAT_PME_RID_LSH 0
+#define PCICAP_EXP_RSTAT_PME_RID 0x0000ffff
#define PCICAP_EXP_RSTAT_PME_STATUS 0x00010000
#define PCICAP_EXP_RSTAT_PME_PENDING 0x00020000
#define PCIECAP_EXP_DCAP2 0x24
-#define PCICAP_EXP_DCAP2_CMPTOUT_MASK 0x0000000f
-#define PCICAP_EXP_DCAP2_CMPTOUT_LSH 0
+#define PCICAP_EXP_DCAP2_CMPTOUT 0x0000000f
#define PCICAP_EXP_DCAP2_CMPTOUT_DIS 0x00000010
#define PCICAP_EXP_DCAP2_ARI_FWD 0x00000020
#define PCICAP_EXP_DCAP2_ATOMIC_RTE 0x00000040
@@ -358,15 +333,13 @@
#define PCICAP_EXP_DCAP2_OBFF_WAKE 0x00080000
#define PCICAP_EXP_DCAP2_EXTFMT 0x00100000
#define PCICAP_EXP_DCAP2_EETLP_PFX 0x00200000
-#define PCICAP_EXP_DCAP2_MAXEETP_MASK 0x00c00000
-#define PCICAP_EXP_DCAP2_MAXEETP_LSH 22
+#define PCICAP_EXP_DCAP2_MAXEETP 0x00c00000
#define PCIE_EETLPP_1 1
#define PCIE_EETLPP_2 2
#define PCIE_EETLPP_3 3
#define PCIE_EETLPP_4 0
#define PCICAP_EXP_DCTL2 0x28
-#define PCICAP_EXP_DCTL2_CMPTOUT_MASK 0x000f
-#define PCICAP_EXP_DCTL2_CMPTOUT_LSH 0
+#define PCICAP_EXP_DCTL2_CMPTOUT 0x000f
#define PCICAP_EXP_DCTL2_CMPTOUT_DIS 0x0010
#define PCICAP_EXP_DCTL2_ARI_FWD 0x0020
#define PCICAP_EXP_DCTL2_ATOMIC_REQ 0x0040
@@ -374,8 +347,7 @@
#define PCICAP_EXP_DCTL2_IDO_REQ 0x0100
#define PCICAP_EXP_DCTL2_IDO_COMPL 0x0200
#define PCICAP_EXP_DCTL2_LTR 0x0400
-#define PCICAP_EXP_DCTL2_OBFF_MASK 0x6000
-#define PCICAP_EXP_DCTL2_OBFF_LSH 13
+#define PCICAP_EXP_DCTL2_OBFF 0x6000
#define PCIE_OBFF_MODE_DISABLED 0
#define PCIE_OBFF_MODE_MSG_A 1
#define PCIE_OBFF_MODE_MSG_B 2
@@ -388,17 +360,14 @@
#define PCICAP_EXP_LCAP2_SP_8d0GTs 0x00000008
#define PCICAP_EXP_LCAP2_XLINK 0x00000100
#define PCICAP_EXP_LCTL2 0x30
-#define PCICAP_EXP_LCTL2_TLSPD_MASK 0x000f
-#define PCICAP_EXP_LCTL2_TLSPD_LSH 0 /* use PCIE_LSPEED_ consts */
+#define PCICAP_EXP_LCTL2_TLSPD 0x000f /* use PCIE_LSPEED_ consts */
#define PCICAP_EXP_LCTL2_ENTER_COMPL 0x0010
#define PCICAP_EXP_LCTL2_HWAUTSPDIS 0x0020
#define PCICAP_EXP_LCTL2_SEL_DEEMPH 0x0040
-#define PCICAP_EXP_LCTL2_XMTMARG_MASK 0x0380
-#define PCICAP_EXP_LCTL2_XMTMARG_LSH 7
+#define PCICAP_EXP_LCTL2_XMTMARG 0x0380
#define PCICAP_EXP_LCTL2_ENTER_MCOMPL 0x0400
#define PCICAP_EXP_LCTL2_COMPL_SOS 0x0800
-#define PCICAP_EXP_LCTL2_CMPPDEM_MASK 0xf000
-#define PCICAP_EXP_LCTL2_CMPPDEM_LSH 12
+#define PCICAP_EXP_LCTL2_CMPPDEM 0xf000
#define PCICAP_EXP_LSTA2 0x32
#define PCICAP_EXP_LSTA2_DEMPH_LVL 0x0001
#define PCICAP_EXP_LSTA2_EQ_COMPLETE 0x0002
@@ -414,12 +383,9 @@
* PCI-E Extended capabilties
*/
#define PCI_CFG_ECAP_START 0x100
-#define PCI_CFG_ECAP_ID_MASK 0x0000ffff
-#define PCI_CFG_ECAP_ID_LSH 0
-#define PCI_CFG_ECAP_VERS_MASK 0x000f0000
-#define PCI_CFG_ECAP_VERS_LSH 16
-#define PCI_CFG_ECAP_NEXT_MASK 0xfff00000
-#define PCI_CFG_ECAP_NEXT_LSH 20
+#define PCI_CFG_ECAP_ID 0x0000ffff
+#define PCI_CFG_ECAP_VERS 0x000f0000
+#define PCI_CFG_ECAP_NEXT 0xfff00000
/* AER Ext. Capability */
#define PCIECAP_ID_AER 0x0001
@@ -484,8 +450,7 @@
#define PCIECAP_AER_CE_MASK_CORTD_INTERNAL 0x00004000
#define PCIECAP_AER_CE_MASK_HDR_LOG_OVFL 0x00008000
#define PCIECAP_AER_CAPCTL 0x18
-#define PCIECAP_AER_CAPCTL_FPTR_MASK 0x0000001f
-#define PCIECAP_AER_CAPCTL_FPTR_LSH 0
+#define PCIECAP_AER_CAPCTL_FPTR 0x0000001f
#define PCIECAP_AER_CAPCTL_ECRCG_CAP 0x00000020
#define PCIECAP_AER_CAPCTL_ECRCG_EN 0x00000040
#define PCIECAP_AER_CAPCTL_ECRCC_CAP 0x00000080
@@ -509,13 +474,10 @@
#define PCIECAP_AER_RERR_F_UFATAL 0x00000010
#define PCIECAP_AER_RERR_NFE 0x00000020
#define PCIECAP_AER_RERR_FE 0x00000040
-#define PCIECAP_AER_RERR_MSINO_MASK 0xf8000000
-#define PCIECAP_AER_RERR_MSINO_LSH 27
+#define PCIECAP_AER_RERR_MSINO 0xf8000000
#define PCIECAP_AER_SRCID 0x34
-#define PCIECAP_AER_SRCID_CORR_MASK 0x0000ffff
-#define PCIECAP_AER_SRCID_CORR_LSH 0
-#define PCIECAP_AER_SRCID_FNF_MASK 0xffff0000
-#define PCIECAP_AER_SRCID_FNF_LSH 16
+#define PCIECAP_AER_SRCID_CORR 0x0000ffff
+#define PCIECAP_AER_SRCID_FNF 0xffff0000
#define PCIECAP_AER_TLP_PFX_LOG0 0x38
#define PCIECAP_AER_TLP_PFX_LOG1 0x3c
#define PCIECAP_AER_TLP_PFX_LOG2 0x40