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author | Christophe Lombard <clombard@linux.vnet.ibm.com> | 2021-10-14 17:56:51 +0200 |
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committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:26:01 +0530 |
commit | 768f67e686e5691a6d6d956f625ce455d3b48fb5 (patch) | |
tree | 5bd43725c341f3c8014c2e0cf3a88f71f61bfa4b /include/pau.h | |
parent | b10c12c63a4f58fe2c31dafdc5269c65b3a8a613 (diff) | |
download | skiboot-768f67e686e5691a6d6d956f625ce455d3b48fb5.zip skiboot-768f67e686e5691a6d6d956f625ce455d3b48fb5.tar.gz skiboot-768f67e686e5691a6d6d956f625ce455d3b48fb5.tar.bz2 |
pau: introduce support
OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable
PHYs, Datalink Layer Logic and Transaction Layer Logic to be included.
The PHYs are the physical connection to the OCAPI interconnect.
The Datalink Layer provides link training.
The Transaction Layer executes the cache coherent and data movement
commands on the P10 chip.
The PAU provides the Transaction Layer functionality for the OCAPI
link(s) on the P10 chip.
The P10 PAU supports two OCAPI links. Six accelerator units PAUs are
instantiated on the P10 chip for a total of twelve OCAPI links.
This patch adds PAU opencapi structure for supporting OpenCapi5.
hw/pau.c file contains main of PAU management functions.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/pau.h')
-rw-r--r-- | include/pau.h | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/include/pau.h b/include/pau.h new file mode 100644 index 0000000..2a26a65 --- /dev/null +++ b/include/pau.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * Copyright 2021 IBM Corp. + */ + +#ifndef __PAU_H +#define __PAU_H + +#include <io.h> +#include <pci.h> +#include <xscom.h> +#include <pau-regs.h> + +#define PAU_NBR 6 +#define PAU_LINKS_OPENCAPI_PER_PAU 2 + +enum pau_dev_type { + PAU_DEV_TYPE_UNKNOWN = 0, + PAU_DEV_TYPE_OPENCAPI, + PAU_DEV_TYPE_ANY = INT_MAX +}; + +struct pau_dev { + enum pau_dev_type type; + uint32_t index; + struct dt_node *dn; + + /* Associated PHY information */ + uint32_t pau_unit; /* 0,3,4,5,6,7 */ + uint32_t odl_index; + uint32_t op_unit; /* 0 -> 7 */ + uint32_t phy_lane_mask; + + struct pau *pau; +}; + +struct pau { + uint32_t index; + struct dt_node *dt_node; + uint32_t chip_id; + uint64_t xscom_base; + + /* Global MMIO window (all PAU regs) */ + uint64_t regs[2]; + + struct lock lock; + + uint32_t links; + struct pau_dev devices[PAU_LINKS_OPENCAPI_PER_PAU]; +}; + +#define PAUDBG(pau, fmt, a...) PAULOG(PR_DEBUG, pau, fmt, ##a) +#define PAUINF(pau, fmt, a...) PAULOG(PR_INFO, pau, fmt, ##a) +#define PAUERR(pau, fmt, a...) PAULOG(PR_ERR, pau, fmt, ##a) + +#define PAUDEVDBG(dev, fmt, a...) PAUDEVLOG(PR_DEBUG, dev, fmt, ##a) +#define PAUDEVINF(dev, fmt, a...) PAUDEVLOG(PR_INFO, dev, fmt, ##a) +#define PAUDEVERR(dev, fmt, a...) PAUDEVLOG(PR_ERR, dev, fmt, ##a) + +#define PAULOG(l, pau, fmt, a...) \ + prlog(l, "PAU[%d:%d]: " fmt, (pau)->chip_id, (pau)->index, ##a) + +#define PAUDEVLOG(l, dev, fmt, a...) \ + prlog(l, "PAU[%d:%d:%d]: " fmt, \ + (dev)->pau->chip_id, \ + (dev)->pau->index, \ + (dev)->index, ##a) + + +/* pau-scope index of the link */ +static inline uint32_t pau_dev_index(struct pau_dev *dev, int links) +{ + return dev->pau->index * links + dev->index; +} + +struct pau_dev *pau_next_dev(struct pau *pau, struct pau_dev *dev, + enum pau_dev_type type); + +#define pau_for_each_dev_type(dev, pau, type) \ + for (dev = NULL; (dev = pau_next_dev(pau, dev, type));) + +#define pau_for_each_opencapi_dev(dev, pau) \ + pau_for_each_dev_type(dev, pau, PAU_DEV_TYPE_OPENCAPI) + +#define pau_for_each_dev(dev, pau) \ + pau_for_each_dev_type(dev, pau, PAU_DEV_TYPE_ANY) + +#define PAU_PHB_INDEX_BASE 6 /* immediately after real PHBs */ +static inline int pau_get_phb_index(unsigned int pau_index, + unsigned int link_index) +{ + return PAU_PHB_INDEX_BASE + pau_index * 2 + link_index; +} + +#endif /* __PAU_H */ |