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| author | Christophe Lombard <clombard@linux.vnet.ibm.com> | 2021-10-14 17:56:53 +0200 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:26:01 +0530 |
| commit | 8baea29fdeaa5eab26c1ca6e3b88e18a3387be96 (patch) | |
| tree | 47cc663b979d4efa98ea7481e498d0dd74326c06 /include/pau-regs.h | |
| parent | faea2419754c0a455b6cf32a5fa58c72fa75083b (diff) | |
| download | skiboot-8baea29fdeaa5eab26c1ca6e3b88e18a3387be96.zip skiboot-8baea29fdeaa5eab26c1ca6e3b88e18a3387be96.tar.gz skiboot-8baea29fdeaa5eab26c1ca6e3b88e18a3387be96.tar.bz2 | |
pau: assign bars
Configure early PAU Global MMIO BAR registers to allow PAU MMIO
register accesses. This is done for each PAU. Enable the Powerbus
interface is mandatory for MMIO accesses.
For each OpenCAPI device, configure the bar registers to access to
the AFU MMIO and to the AFU Config Addr/Data registers.
AFU Config/Data registers = GENID_ADDR (from phy_map file) + 320K
(= 0x50000)
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/pau-regs.h')
| -rw-r--r-- | include/pau-regs.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/include/pau-regs.h b/include/pau-regs.h index a35668f..afe6f95 100644 --- a/include/pau-regs.h +++ b/include/pau-regs.h @@ -26,5 +26,31 @@ #define PAU_REG_OFFSET(reg) ((reg) & 0xffff) #define PAU_BLOCK_CQ_SM(n) PAU_BLOCK(4, (n)) +#define PAU_BLOCK_CQ_CTL PAU_BLOCK(4, 4) + +/* + * CQ_SM block registers + * + * Definitions here use PAU_BLOCK_CQ_SM(0), but when pau_write() is given + * one of these, it will do corresponding writes to every CQ_SM block. + */ +#define PAU_MCP_MISC_CFG0 (PAU_BLOCK_CQ_SM(0) + 0x000) +#define PAU_MCP_MISC_CFG0_MA_MCRESP_OPT_WRP PPC_BIT(9) +#define PAU_MCP_MISC_CFG0_ENABLE_PBUS PPC_BIT(26) +#define PAU_SNP_MISC_CFG0 (PAU_BLOCK_CQ_SM(0) + 0x180) +#define PAU_SNP_MISC_CFG0_ENABLE_PBUS PPC_BIT(2) +#define PAU_NTL_BAR(brk) (PAU_BLOCK_CQ_SM(0) + 0x1b8 + (brk) * 8) +#define PAU_NTL_BAR_ADDR PPC_BITMASK(3, 35) +#define PAU_NTL_BAR_SIZE PPC_BITMASK(39, 43) +#define PAU_MMIO_BAR (PAU_BLOCK_CQ_SM(0) + 0x1e0) +#define PAU_MMIO_BAR_ENABLE PPC_BIT(0) +#define PAU_MMIO_BAR_ADDR PPC_BITMASK(3, 27) +#define PAU_GENID_BAR (PAU_BLOCK_CQ_SM(0) + 0x1e8) +#define PAU_GENID_BAR_ADDR PPC_BITMASK(3, 32) + +/* CQ_CTL block registers */ +#define PAU_CTL_MISC_MMIOPA_CONFIG(brk) (PAU_BLOCK_CQ_CTL + 0x098 + (brk) * 8) +#define PAU_CTL_MISC_MMIOPA_CONFIG_BAR_ADDR PPC_BITMASK(1, 35) +#define PAU_CTL_MISC_MMIOPA_CONFIG_BAR_SIZE PPC_BITMASK(39, 43) #endif /* __PAU_REGS_H */ |