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authorDan Streetman <ddstreet@ieee.org>2015-03-09 21:26:27 -0400
committerStewart Smith <stewart@linux.vnet.ibm.com>2015-03-17 16:29:25 +1100
commit88688d382533fb3cfb1422050481862afd6534df (patch)
tree0aa177982c93865901f0a3ceb8f64b1ca62d6e4a /include/nx.h
parent62aaaec7ab3c84c2226d5a89a5beb787a2e085f0 (diff)
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Add NX P7+ support
Add NX config register values for P7+. Remove "P8" from all register defines, where the define is common to P7+ and P8. For values new to P8 (specifically 842 prefeching), only enable on P8. This should correctly setup the NX coprocessors on P7+ systems. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/nx.h')
-rw-r--r--include/nx.h131
1 files changed, 68 insertions, 63 deletions
diff --git a/include/nx.h b/include/nx.h
index 45344da..cf887c0 100644
--- a/include/nx.h
+++ b/include/nx.h
@@ -21,75 +21,80 @@
/* Register addresses and bit fields */
/*************************************/
+#define NX_P7_SAT(sat, offset) XSCOM_SAT(0x1, sat, offset)
+#define NX_P8_SAT(sat, offset) XSCOM_SAT(0xc, sat, offset)
+
/* Random Number Generator */
-#define NX_P7_RNG_BAR XSCOM_SAT(0x1, 0x2, 0x0c)
+#define NX_P7_RNG_BAR NX_P7_SAT(0x2, 0x0c)
+#define NX_P8_RNG_BAR NX_P8_SAT(0x2, 0x0d)
#define NX_P7_RNG_BAR_ADDR PPC_BITMASK(18, 51)
-#define NX_P7_RNG_BAR_SIZE PPC_BITMASK(53, 55)
-#define NX_P7_RNG_BAR_ENABLE PPC_BIT(52)
-#define NX_P8_RNG_BAR XSCOM_SAT(0xc, 0x2, 0x0d)
#define NX_P8_RNG_BAR_ADDR PPC_BITMASK(14, 51)
-#define NX_P8_RNG_BAR_SIZE PPC_BITMASK(53, 55)
-#define NX_P8_RNG_BAR_ENABLE PPC_BIT(52)
+#define NX_RNG_BAR_SIZE PPC_BITMASK(53, 55)
+#define NX_RNG_BAR_ENABLE PPC_BIT(52)
-#define NX_P7_RNG_CFG XSCOM_SAT(0x1, 0x2, 0x12)
-#define NX_P7_RNG_CFG_ENABLE PPC_BIT(63)
-#define NX_P8_RNG_CFG XSCOM_SAT(0xc, 0x2, 0x12)
-#define NX_P8_RNG_CFG_ENABLE PPC_BIT(63)
+#define NX_P7_RNG_CFG NX_P7_SAT(0x2, 0x12)
+#define NX_P8_RNG_CFG NX_P8_SAT(0x2, 0x12)
+#define NX_RNG_CFG_ENABLE PPC_BIT(63)
/* Symmetric Crypto */
-#define NX_P8_SYM_CFG XSCOM_SAT(0xc, 0x2, 0x0a)
-#define NX_P8_SYM_CFG_CI PPC_BITMASK(2, 14)
-#define NX_P8_SYM_CFG_CT PPC_BITMASK(18, 23)
-#define NX_P8_SYM_CFG_FC_ENABLE PPC_BITMASK(32, 39)
-#define NX_P8_SYM_CFG_ENABLE PPC_BIT(63)
+#define NX_P7_SYM_CFG NX_P7_SAT(0x2, 0x09)
+#define NX_P8_SYM_CFG NX_P8_SAT(0x2, 0x0a)
+#define NX_SYM_CFG_CI PPC_BITMASK(2, 14)
+#define NX_SYM_CFG_CT PPC_BITMASK(18, 23)
+#define NX_SYM_CFG_FC_ENABLE PPC_BITMASK(32, 39)
+#define NX_SYM_CFG_ENABLE PPC_BIT(63)
/* Asymmetric Crypto */
-#define NX_P8_ASYM_CFG XSCOM_SAT(0xc, 0x2, 0x0b)
-#define NX_P8_ASYM_CFG_CI PPC_BITMASK(2, 14)
-#define NX_P8_ASYM_CFG_CT PPC_BITMASK(18, 23)
-#define NX_P8_ASYM_CFG_FC_ENABLE PPC_BITMASK(32, 52)
-#define NX_P8_ASYM_CFG_ENABLE PPC_BIT(63)
+#define NX_P7_ASYM_CFG NX_P7_SAT(0x2, 0x0a)
+#define NX_P8_ASYM_CFG NX_P8_SAT(0x2, 0x0b)
+#define NX_ASYM_CFG_CI PPC_BITMASK(2, 14)
+#define NX_ASYM_CFG_CT PPC_BITMASK(18, 23)
+#define NX_ASYM_CFG_FC_ENABLE PPC_BITMASK(32, 52)
+#define NX_ASYM_CFG_ENABLE PPC_BIT(63)
/* 842 Compression */
-#define NX_P8_842_CFG XSCOM_SAT(0xc, 0x2, 0x0c)
-#define NX_P8_842_CFG_CI PPC_BITMASK(2, 14)
-#define NX_P8_842_CFG_CT PPC_BITMASK(18, 23)
-#define NX_P8_842_CFG_FC_ENABLE PPC_BITMASK(32, 36)
-#define NX_P8_842_CFG_ENABLE PPC_BIT(63)
+#define NX_P7_842_CFG NX_P7_SAT(0x2, 0x0b)
+#define NX_P8_842_CFG NX_P8_SAT(0x2, 0x0c)
+#define NX_842_CFG_CI PPC_BITMASK(2, 14)
+#define NX_842_CFG_CT PPC_BITMASK(18, 23)
+#define NX_842_CFG_FC_ENABLE PPC_BITMASK(32, 36)
+#define NX_842_CFG_ENABLE PPC_BIT(63)
/* DMA */
-#define NX_P8_DMA_CFG XSCOM_SAT(0xc, 0x1, 0x02)
-#define NX_P8_DMA_CFG_842_COMPRESS_PREFETCH PPC_BIT(23)
-#define NX_P8_DMA_CFG_842_DECOMPRESS_PREFETCH PPC_BIT(24)
-#define NX_P8_DMA_CFG_AES_SHA_MAX_RR PPC_BITMASK(25, 28)
-#define NX_P8_DMA_CFG_AMF_MAX_RR PPC_BITMASK(29, 32)
-#define NX_P8_DMA_CFG_842_COMPRESS_MAX_RR PPC_BITMASK(33, 36)
-#define NX_P8_DMA_CFG_842_DECOMPRESS_MAX_RR PPC_BITMASK(37, 40)
-#define NX_P8_DMA_CFG_AES_SHA_CSB_WR PPC_BITMASK(41, 42)
-#define NX_P8_DMA_CFG_AES_SHA_COMPLETION_MODE PPC_BITMASK(43, 44)
-#define NX_P8_DMA_CFG_AES_SHA_CPB_WR PPC_BITMASK(45, 46)
-#define NX_P8_DMA_CFG_AES_SHA_OUTPUT_DATA_WR PPC_BIT(47)
-#define NX_P8_DMA_CFG_AMF_CSB_WR PPC_BITMASK(49, 50)
-#define NX_P8_DMA_CFG_AMF_COMPLETION_MODE PPC_BITMASK(51, 52)
-#define NX_P8_DMA_CFG_AMF_CPB_WR PPC_BITMASK(53, 54)
-#define NX_P8_DMA_CFG_AMF_OUTPUT_DATA_WR PPC_BIT(55)
-#define NX_P8_DMA_CFG_842_SPBC PPC_BIT(56)
-#define NX_P8_DMA_CFG_842_CSB_WR PPC_BITMASK(57, 58)
-#define NX_P8_DMA_CFG_842_COMPLETION_MODE PPC_BITMASK(59, 60)
-#define NX_P8_DMA_CFG_842_CPB_WR PPC_BITMASK(61, 62)
-#define NX_P8_DMA_CFG_842_OUTPUT_DATA_WR PPC_BIT(63)
+#define NX_P7_DMA_CFG NX_P7_SAT(0x1, 0x02)
+#define NX_P8_DMA_CFG NX_P8_SAT(0x1, 0x02)
+#define NX_P8_DMA_CFG_842_COMPRESS_PREFETCH PPC_BIT(23)
+#define NX_P8_DMA_CFG_842_DECOMPRESS_PREFETCH PPC_BIT(24)
+#define NX_DMA_CFG_AES_SHA_MAX_RR PPC_BITMASK(25, 28)
+#define NX_DMA_CFG_AMF_MAX_RR PPC_BITMASK(29, 32)
+#define NX_DMA_CFG_842_COMPRESS_MAX_RR PPC_BITMASK(33, 36)
+#define NX_DMA_CFG_842_DECOMPRESS_MAX_RR PPC_BITMASK(37, 40)
+#define NX_DMA_CFG_AES_SHA_CSB_WR PPC_BITMASK(41, 42)
+#define NX_DMA_CFG_AES_SHA_COMPLETION_MODE PPC_BITMASK(43, 44)
+#define NX_DMA_CFG_AES_SHA_CPB_WR PPC_BITMASK(45, 46)
+#define NX_DMA_CFG_AES_SHA_OUTPUT_DATA_WR PPC_BIT(47)
+#define NX_DMA_CFG_AMF_CSB_WR PPC_BITMASK(49, 50)
+#define NX_DMA_CFG_AMF_COMPLETION_MODE PPC_BITMASK(51, 52)
+#define NX_DMA_CFG_AMF_CPB_WR PPC_BITMASK(53, 54)
+#define NX_DMA_CFG_AMF_OUTPUT_DATA_WR PPC_BIT(55)
+#define NX_DMA_CFG_842_SPBC PPC_BIT(56)
+#define NX_DMA_CFG_842_CSB_WR PPC_BITMASK(57, 58)
+#define NX_DMA_CFG_842_COMPLETION_MODE PPC_BITMASK(59, 60)
+#define NX_DMA_CFG_842_CPB_WR PPC_BITMASK(61, 62)
+#define NX_DMA_CFG_842_OUTPUT_DATA_WR PPC_BIT(63)
/* Engine Enable Register */
-#define NX_P8_EE_CFG XSCOM_SAT(0xc, 0x1, 0x01)
-#define NX_P8_EE_CFG_EFUSE PPC_BIT(0)
-#define NX_P8_EE_CFG_AMF_3 PPC_BIT(53)
-#define NX_P8_EE_CFG_AMF_2 PPC_BIT(54)
-#define NX_P8_EE_CFG_AMF_1 PPC_BIT(55)
-#define NX_P8_EE_CFG_AMF_0 PPC_BIT(56)
-#define NX_P8_EE_CFG_SYM_1 PPC_BIT(57)
-#define NX_P8_EE_CFG_SYM_0 PPC_BIT(58)
-#define NX_P8_EE_CFG_842_1 PPC_BIT(62)
-#define NX_P8_EE_CFG_842_0 PPC_BIT(63)
+#define NX_P7_EE_CFG NX_P7_SAT(0x1, 0x01)
+#define NX_P8_EE_CFG NX_P8_SAT(0x1, 0x01)
+#define NX_EE_CFG_EFUSE PPC_BIT(0)
+#define NX_EE_CFG_CH7 PPC_BIT(53) /* AMF */
+#define NX_EE_CFG_CH6 PPC_BIT(54) /* AMF */
+#define NX_EE_CFG_CH5 PPC_BIT(55) /* AMF */
+#define NX_EE_CFG_CH4 PPC_BIT(56) /* P7: SYM, P8: AMF */
+#define NX_EE_CFG_CH3 PPC_BIT(57) /* SYM */
+#define NX_EE_CFG_CH2 PPC_BIT(58) /* SYM */
+#define NX_EE_CFG_CH1 PPC_BIT(62) /* 842 */
+#define NX_EE_CFG_CH0 PPC_BIT(63) /* 842 */
/**************************************/
@@ -102,18 +107,18 @@
#define NX_CT_842 (3)
/* Coprocessor Instance counter
- * P8 NX workbook, section 5.5.1
+ * NX workbook, section 5.5.1
* "Assigning <CT,CI> Values"
*/
-#define NX_P8_SYM_CFG_CI_MAX (511)
-#define NX_P8_SYM_CFG_CI_LSHIFT (2)
-#define NX_P8_ASYM_CFG_CI_MAX (127)
-#define NX_P8_ASYM_CFG_CI_LSHIFT (4)
-#define NX_P8_842_CFG_CI_MAX (511)
-#define NX_P8_842_CFG_CI_LSHIFT (2)
+#define NX_SYM_CFG_CI_MAX (511)
+#define NX_SYM_CFG_CI_LSHIFT (2)
+#define NX_ASYM_CFG_CI_MAX (127)
+#define NX_ASYM_CFG_CI_LSHIFT (4)
+#define NX_842_CFG_CI_MAX (511)
+#define NX_842_CFG_CI_LSHIFT (2)
/* DMA configuration values
- * P8 NX workbook, section 5.2.3, table 5-4
+ * NX workbook, section 5.2.3, table 5-4
* "DMA Configuration Register Bits"
*
* These values can be used for the AES/SHA, AMF, and 842 DMA