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| author | Haren Myneni <haren@linux.vnet.ibm.com> | 2018-06-06 00:38:20 -0700 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2018-06-18 22:13:13 -0500 |
| commit | 56026a13292453b072ad3cc9adf3dee960077f38 (patch) | |
| tree | 164f5050f2fedb90c2d3b330d3f3b1c93a9a183d /include/nx.h | |
| parent | 94140dbc6a9cafd868609567f944349a1ed5cfe4 (diff) | |
| download | skiboot-56026a13292453b072ad3cc9adf3dee960077f38.zip skiboot-56026a13292453b072ad3cc9adf3dee960077f38.tar.gz skiboot-56026a13292453b072ad3cc9adf3dee960077f38.tar.bz2 | |
NX: Add NX coprocessor init opal call
The read offset (4:11) in Receive FIFO control register is incremented
by FIFO size whenever CRB read by NX. But the index in RxFIFO has to
match with the corresponding entry in FIFO maintained by VAS in kernel.
VAS entry is reset to 0 when opening the receive window during driver
initialization. So when NX842 is reloaded or in kexec boot, possibility
of mismatch between RxFIFO control register and VAS entries in kernel.
It could cause CRB failure / timeout from NX.
This patch adds nx_coproc_init opal call for kernel to initialize
readOffset (4:11) and Queued (15:23) in RxFIFO control register.
Fixes: 3b3c5962f432 ("NX: Add P9 NX support for 842 compression engine")
CC: stable # v5.8+
Signed-off-by: Haren Myneni <haren@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include/nx.h')
| -rw-r--r-- | include/nx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/nx.h b/include/nx.h index c2f7dfc..0322349 100644 --- a/include/nx.h +++ b/include/nx.h @@ -149,6 +149,7 @@ #define NX_P9_GZIP_HIGH_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x05) #define NX_P9_842_NORMAL_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x0c) #define NX_P9_GZIP_NORMAL_PRI_RX_FIFO_CTRL NX_P9_SAT(0x3, 0x0e) +#define NX_P9_RX_FIFO_CTRL_READ_OFFSET PPC_BITMASK(4, 11) #define NX_P9_RX_FIFO_CTRL_QUEUED PPC_BITMASK(15, 23) #define NX_P9_RX_FIFO_CTRL_HPRI_MAX_READ PPC_BITMASK(27, 35) |