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author | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-02-28 17:52:12 +1100 |
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committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-02-28 20:28:39 -0600 |
commit | fbdc91e693fc3103f7e2a65054ed32bfb26a2e17 (patch) | |
tree | d3f6b3335d631ec42afde41941e2ba53a3213188 /include/npu2-regs.h | |
parent | 18d7ee718bef3c95787473e3537be5f0653470c4 (diff) | |
download | skiboot-fbdc91e693fc3103f7e2a65054ed32bfb26a2e17.zip skiboot-fbdc91e693fc3103f7e2a65054ed32bfb26a2e17.tar.gz skiboot-fbdc91e693fc3103f7e2a65054ed32bfb26a2e17.tar.bz2 |
NPU2 HMIs: dump out a *LOT* of npu2 registers for debugging
This is not the way we want to end up doing this.
This is a hack to make folk happy and not require crondump to
debug nvidia/npu2 issues.
Cc: stable
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/npu2-regs.h')
-rw-r--r-- | include/npu2-regs.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index c109273..73925f9 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -1,4 +1,4 @@ -/* Copyright 2013-2016 IBM Corp. +/* Copyright 2013-2018 IBM Corp. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -24,6 +24,10 @@ uint64_t npu2_read(struct npu2 *p, uint64_t reg); void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val); void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); +/* SCOM Registers to dump on HMI to aid in debugging */ +#define NPU2_DEBUG_REG_START 0x5011000 +#define NPU2_DEBUG_REG_END 0x50110FF + /* These aren't really NPU specific registers but we initialise them in NPU * code */ #define MCD0_BANK0_CN3 0x301100d @@ -468,6 +472,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_FIR_REGISTER_0 0x0000000005013C00 #define NPU2_FIR_REGISTER_1 0x0000000005013C40 #define NPU2_FIR_REGISTER_2 0x0000000005013C80 +#define NPU2_FIR_REGISTER_END 0x0000000005013CFF #define NPU2_TOTAL_FIR_REGISTERS 3 |