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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2019-04-05 16:33:03 +0200 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-04-09 10:50:55 +1000 |
| commit | d1f3e4faf9d99d76bc413503afea87c8486af8b1 (patch) | |
| tree | 5ae00584124d92e2193762e100abe289c26c23e6 /include/npu2-regs.h | |
| parent | 7320a21e7261d5ed87971a7985fecdd7588a72ec (diff) | |
| download | skiboot-d1f3e4faf9d99d76bc413503afea87c8486af8b1.zip skiboot-d1f3e4faf9d99d76bc413503afea87c8486af8b1.tar.gz skiboot-d1f3e4faf9d99d76bc413503afea87c8486af8b1.tar.bz2 | |
hw/npu2: Dump (more) npu2 registers on link error and HMIs
We were already logging some NPU registers during an HMI. This patch
cleans up a bit how it is done and separates what is global from what
is specific to nvlink or opencapi.
Since we can now receive an error interrupt when an opencapi link goes
down unexpectedly, we also dump the NPU state but we limit it to the
registers of the brick which hit the error.
The list of registers to dump was worked out with the hw team to
allow for proper debugging. For each register, we print the name as
found in the NPU workbook, the scom address and the register value.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include/npu2-regs.h')
| -rw-r--r-- | include/npu2-regs.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 939a23f..ba10b8e 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -203,6 +203,8 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_PERF_MASK 0x110 #define NPU2_DBG0_CFG 0x118 #define NPU2_DBG1_CFG 0x120 +#define NPU2_C_ERR_RPT_MSG5 0x128 +#define NPU2_C_ERR_RPT_MSG6 0x130 /* CTL block registers */ #define NPU2_CQ_CTL_MISC_CFG 0x000 @@ -295,10 +297,12 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_NTL_MISC_CFG3(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x008) #define NPU2_NTL_ERR_HOLD1(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x010) #define NPU2_NTL_ERR_MASK1(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x018) +#define NPU2_NTL_ERR_FIRST1_OFF 0x020 #define NPU2_NTL_ERR_FIRST1(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x020) #define NPU2_NTL_ERR_FIRST1_MASK(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x028) #define NPU2_NTL_ERR_HOLD2(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x030) #define NPU2_NTL_ERR_MASK2(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x038) +#define NPU2_NTL_ERR_FIRST2_OFF 0x040 #define NPU2_NTL_ERR_FIRST2(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x040) #define NPU2_NTL_ERR_FIRST2_MASK(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x048) #define NPU2_NTL_SCRATCH2(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x050) @@ -402,6 +406,12 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_OTL_OSL_DAR(stack, block) NPU2_REG_OFFSET(stack, block, 0x008) #define NPU2_OTL_OSL_TFC(stack, block) NPU2_REG_OFFSET(stack, block, 0x010) #define NPU2_OTL_OSL_PEHANDLE(stack, block) NPU2_REG_OFFSET(stack, block, 0x018) +#define NPU2_OTL_ERR_RPT_HOLD0 0x30 +#define NPU2_OTL_RAS_ERR_MSG0 0x68 +#define NPU2_OTL_RXI_ERR_SIG 0x70 +#define NPU2_OTL_RXO_ERR_SIG 0x78 +#define NPU2_OTL_ERR_RPT_HOLD1 0xB0 + /* Misc block registers. Unlike the SM/CTL/DAT/NTL registers above * there is only a single instance of each of these in the NPU so we |