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| author | Reza Arbab <arbab@linux.ibm.com> | 2018-08-01 15:01:18 -0500 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2018-08-06 03:00:59 -0500 |
| commit | 736d8b150f8611af0c4d0bdf6b3273a7a0e2b1c2 (patch) | |
| tree | 68751308d7b6057b0df524f06ea16c2ded4078e1 /include/npu2-regs.h | |
| parent | f43465a0ac6da0e2f120c227e103497cb35cc8c4 (diff) | |
| download | skiboot-736d8b150f8611af0c4d0bdf6b3273a7a0e2b1c2.zip skiboot-736d8b150f8611af0c4d0bdf6b3273a7a0e2b1c2.tar.gz skiboot-736d8b150f8611af0c4d0bdf6b3273a7a0e2b1c2.tar.bz2 | |
npu2: Add support for relaxed-ordering mode
Some device drivers support out of order access to GPU memory. This does
not affect the CPU view of memory but it does affect the GPU view of
memory. It should only be enabled if the GPU driver has requested it.
Add OPAL APIs allowing the driver to query relaxed ordering state or
request it to be set for a device. Current hardware only allows relaxed
ordering to be enabled per PCIe root port. So the code here doesn't
enable relaxed ordering until it has been explicitly requested for every
device on the port.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
[arbab@linux.ibm.com: Rebase/refactor original changes]
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-By: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include/npu2-regs.h')
| -rw-r--r-- | include/npu2-regs.h | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index d9db988..6bd77e4 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -152,9 +152,24 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_LOW_WATER_MARKS 0x040 #define NPU2_LOW_WATER_MARKS_ENABLE_MACHINE_ALLOC PPC_BIT(51) #define NPU2_HIGH_WATER_MARKS 0x048 -#define NPU2_RELAXED_ORDERING_CFG0 0x050 -#define NPU2_RELAXED_ORDERING_CFG1 0x058 -#define NPU2_RELAXED_ORDERING_CFG2 0x060 +#define NPU2_RELAXED_ORDERING_CFG(n) (0x050 + (n)*8) +#define NPU2_RELAXED_ORDERING_SOURCE(n) (PPC_BITMASK(0,31) >> ((n)*32)) +#define NPU2_RELAXED_ORDERING_SOURCE_ENA PPC_BITMASK32(0,3) +#define NPU2_RELAXED_ORDERING_SOURCE_WRENA PPC_BIT32(0) +#define NPU2_RELAXED_ORDERING_SOURCE_RDENA PPC_BIT32(1) +#define NPU2_RELAXED_ORDERING_SOURCE_AWENA PPC_BIT32(2) +#define NPU2_RELAXED_ORDERING_SOURCE_ARENA PPC_BIT32(3) +#define NPU2_RELAXED_ORDERING_SOURCE_PECSEL PPC_BITMASK32(4,5) +#define NPU2_RELAXED_ORDERING_SOURCE_GRPCHP PPC_BITMASK32(6,9) +#define NPU2_RELAXED_ORDERING_SOURCE_WRMIN PPC_BITMASK32(10,14) +#define NPU2_RELAXED_ORDERING_SOURCE_WRMAX PPC_BITMASK32(15,19) +#define NPU2_RELAXED_ORDERING_SOURCE_RDMIN PPC_BITMASK32(20,25) +#define NPU2_RELAXED_ORDERING_SOURCE_RDMAX PPC_BITMASK32(26,31) +#define NPU2_RELAXED_ORDERING_CMD_CL_DMA_W PPC_BIT(0) +#define NPU2_RELAXED_ORDERING_CMD_CL_DMA_W_HP PPC_BIT(1) +#define NPU2_RELAXED_ORDERING_CMD_CL_DMA_INJ PPC_BIT(2) +#define NPU2_RELAXED_ORDERING_CMD_PR_DMA_INJ PPC_BIT(3) +#define NPU2_RELAXED_ORDERING_CMD_DMA_PR_W PPC_BIT(4) #define NPU2_RELAXED_ORDERING_CMD_CL_RD_NC_F0 PPC_BIT(5) #define NPU2_RELAXED_ORDERING_SOURCE4_RDENA PPC_BIT(29) #define NPU2_NTL0_BAR 0x068 |