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| author | Anju T Sudhakar <anju@linux.vnet.ibm.com> | 2021-08-04 12:51:04 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:23:59 +0530 |
| commit | eb9047292b0d3604ed31c09e8d0501615c8ce8a8 (patch) | |
| tree | c67443341fb3305d7bd03e881b1626aeccd66d8e /include/imc.h | |
| parent | 8e5d736cb87ff7577df8b8008bf364693f48b614 (diff) | |
| download | skiboot-eb9047292b0d3604ed31c09e8d0501615c8ce8a8.zip skiboot-eb9047292b0d3604ed31c09e8d0501615c8ce8a8.tar.gz skiboot-eb9047292b0d3604ed31c09e8d0501615c8ce8a8.tar.bz2 | |
hw/imc: Power10 support
POWER10 IMC support:
Add POWER10 scom addresses for IMC
Add support for IMC trace-mode
Fix the catalog subit for POWER10
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/imc.h')
| -rw-r--r-- | include/imc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/imc.h b/include/imc.h index a446dc5..96f9ec4 100644 --- a/include/imc.h +++ b/include/imc.h @@ -110,6 +110,7 @@ struct imc_chip_cb * Core IMC SCOMs */ #define CORE_IMC_EVENT_MASK_ADDR_P9 0x20010AA8ull +#define CORE_IMC_EVENT_MASK_ADDR_P10 0x20020400ull #define CORE_IMC_EVENT_MASK 0x0402010000000000ull #define CORE_IMC_PDBAR_MASK 0x0003ffffffffe000ull #define CORE_IMC_HTM_MODE_ENABLE 0xE800000000000000ull @@ -133,6 +134,7 @@ struct imc_chip_cb * *CPMC1SEL *CPMC2SEL *BUFFERSIZE */ #define TRACE_IMC_ADDR_P9 0x20010AA9ull +#define TRACE_IMC_ADDR_P10 0x20020401ull #define TRACE_IMC_SAMPLESEL(x) ((uint64_t)x << 62) #define TRACE_IMC_CPMC_LOAD(x) ((0xffffffff - (uint64_t)x) << 30) #define TRACE_IMC_CPMC1SEL(x) ((uint64_t)x << 23) |