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| author | Anju T Sudhakar <anju@linux.vnet.ibm.com> | 2017-06-22 17:45:22 +0530 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-06-27 18:45:30 +1000 |
| commit | 7801be0fcf2a2dc306f611934e5559a5218f6a87 (patch) | |
| tree | b6c924dade5b4c89b4098ef8209d1cc2d9887502 /include/imc.h | |
| parent | f98d59958db19f85154dfa36db8f5c7322148294 (diff) | |
| download | skiboot-7801be0fcf2a2dc306f611934e5559a5218f6a87.zip skiboot-7801be0fcf2a2dc306f611934e5559a5218f6a87.tar.gz skiboot-7801be0fcf2a2dc306f611934e5559a5218f6a87.tar.bz2 | |
skiboot: Add opal calls to init/start/stop IMC devices
Add new opal calls to init, start and stop the IMC nest/core units.
To initialize the core IMC counters, it takes a physical address per
core as an input and writes that address to PDBAR[14:50] bits.
It initializes the htm_mode and event_mask, where it selects the time
interval at which the counter values must be posted to the given memory
location and enables the counters to start running by setting the
appropriate bits.
To disable/enable the nest IMC counters (stop or resume counting),
writes into "command" field of the nest control block in the reserve
memory location. To disable/enable the core IMC counters (stop or
resume counting), writes into appropriate bits of htm_mode to
disable the counters.
Acked-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com>
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
[stewart@linux.vnet.ibm.com: use pr_fmt rather than hardcode IMC prefix]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include/imc.h')
| -rw-r--r-- | include/imc.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/imc.h b/include/imc.h index fcd220d..d4381bb 100644 --- a/include/imc.h +++ b/include/imc.h @@ -121,6 +121,15 @@ struct imc_chip_cb #define MAX_NEST_UNITS 48 +/* + * Core IMC SCOMs + */ +#define CORE_IMC_EVENT_MASK_ADDR 0x20010AA8ull +#define CORE_IMC_EVENT_MASK 0x0001020000000000ull +#define CORE_IMC_PDBAR_MASK 0x0003ffffffffe000ull +#define CORE_IMC_HTM_MODE_ENABLE 0xE800000000000000ull +#define CORE_IMC_HTM_MODE_DISABLE 0xE000000000000000ull + void imc_init(void); void imc_catalog_preload(void); #endif /* __IMC_H */ |