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| author | Anju T Sudhakar <anju@linux.vnet.ibm.com> | 2021-06-25 11:49:35 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-06-30 15:05:55 +0530 |
| commit | 713466f9aaba53116ad4d9a6ed5235e5d6615c3f (patch) | |
| tree | de0e3089ace76885a77a548ba60696ce63dedcd6 /include/imc.h | |
| parent | 2c43e32c837b72bea12be08315d69f0a0f2360ba (diff) | |
| download | skiboot-713466f9aaba53116ad4d9a6ed5235e5d6615c3f.zip skiboot-713466f9aaba53116ad4d9a6ed5235e5d6615c3f.tar.gz skiboot-713466f9aaba53116ad4d9a6ed5235e5d6615c3f.tar.bz2 | |
hw/imc: Cleanup code to define scom addr for IMC at run time
Currently scom addresses for IMC are defined at compile time.
The scom addresses may vary for different processor generations.
So clean up the code to pick the right scom addresses, based on
the processor version at run time.
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/imc.h')
| -rw-r--r-- | include/imc.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/imc.h b/include/imc.h index 7aae792..a446dc5 100644 --- a/include/imc.h +++ b/include/imc.h @@ -109,7 +109,7 @@ struct imc_chip_cb /* * Core IMC SCOMs */ -#define CORE_IMC_EVENT_MASK_ADDR 0x20010AA8ull +#define CORE_IMC_EVENT_MASK_ADDR_P9 0x20010AA8ull #define CORE_IMC_EVENT_MASK 0x0402010000000000ull #define CORE_IMC_PDBAR_MASK 0x0003ffffffffe000ull #define CORE_IMC_HTM_MODE_ENABLE 0xE800000000000000ull @@ -132,7 +132,7 @@ struct imc_chip_cb * | | | * *CPMC1SEL *CPMC2SEL *BUFFERSIZE */ -#define TRACE_IMC_ADDR 0x20010AA9ull +#define TRACE_IMC_ADDR_P9 0x20010AA9ull #define TRACE_IMC_SAMPLESEL(x) ((uint64_t)x << 62) #define TRACE_IMC_CPMC_LOAD(x) ((0xffffffff - (uint64_t)x) << 30) #define TRACE_IMC_CPMC1SEL(x) ((uint64_t)x << 23) |