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| author | Ananth N Mavinakayanahalli <ananth@in.ibm.com> | 2014-07-24 11:46:58 +0530 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2014-07-25 14:10:51 +1000 |
| commit | cad0d16e236bcbf457406023d5df4da8d55b778f (patch) | |
| tree | b63b5f3e36fba1a0bc4be4f8daf308b7b113b2c8 /include/fsp.h | |
| parent | 99608f2074d4c8877c8445e20a1275dc1257079c (diff) | |
| download | skiboot-cad0d16e236bcbf457406023d5df4da8d55b778f.zip skiboot-cad0d16e236bcbf457406023d5df4da8d55b778f.tar.gz skiboot-cad0d16e236bcbf457406023d5df4da8d55b778f.tar.bz2 | |
FSP: Rework the R/R state machine
a. Do not trigger PSI link down on DISR's RR bit set.
b. Do trigger HIR if DISR's Unit Check bit is set.
c. On fsp_mbx_err, trigger a HIR (very rare occurance).
d. Use fsp_start_rr() when the DISR's RR bit is seen so all mbox activity is
stopped when the FSP indicates an RR start.
We do not bring the link down voluntarily on DISR's RR begin, pending a
PSI interrupt, which actually triggers the link down. Per Dean Sanner, this
is the right protocol to follow.
The assumption is that a DISR RR bit set would cause a PSI interrupt 'soon'.
One TODO is to figure out if this interrupt never arrives.
The PSI interrupt does come through albeit after a short while:
SURV: [ 1dc662ef7f] Sending the hearbeat command to FSP
SURV: Received heartbeat acknowledge from FSP
FSP #0: DISR stat change = 0x000000a1
FSP #0: FSP in Reset. Waiting for PSI interrupt
FSPCON: Closed consoles on account of FSP reset/reload
SURV: Disabling surveillance
FSP: Closing NVRAM on account of FSP Reset
FSP #0: HDES stat change = 0xffffffff
PSI[0x000]: PSI mgmnt interrupt CR=0xfcf0d100c0000000
PSI: PSI Reported Error
PSI: PSI Link Inactive Transition
PSI: SEMR set to fff0fff00000
PSI[0x000]: Disabling link!
PSI: PSIHB_CR (error bits) set to 68f0510040000000
PSI: starting link polling
PSI: Spurious interrupt, attempting clear
PSI[0x001]: Poll CR=0x00f0100000000000
PSI[0x000]: Poll CR=0x68f0100040000000
PSI[0x001]: Poll CR=0x00f0100000000000
PSI[0x000]: Poll CR=0x68f0100040000000
...
And we recover:
PSI[0x000]: Poll CR=0x68f0100040000000
PSI[0x001]: Poll CR=0xccf0300000000000
PSI[0x001]: Found active link!
PSI: stopping link polling
FSP: Connected to FSP-A
FSP #0: DISR stat change = 0x000000a9
FSP #0: DISR stat change = 0x00000281
FSP #0: Detected R&R complete, acking
FSP #0: HDES stat change = 0x00000000
FSP #0: DISR stat change = 0x00000081
FSP: FSP assuming new role
FSP: SP says Reset/Reload complete
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'include/fsp.h')
| -rw-r--r-- | include/fsp.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/fsp.h b/include/fsp.h index ec25384..b48f4e1 100644 --- a/include/fsp.h +++ b/include/fsp.h @@ -104,6 +104,7 @@ #define FSP_DISR_CLR_REG 0x0C /* Bit masks for DISR */ +#define FSP_DISR_FSP_UNIT_CHECK PPC_BIT32(16) #define FSP_DISR_FSP_RR_COMPLETE PPC_BIT32(22) #define FSP_DISR_RUNTIME_STATE_SYNCD PPC_BIT32(24) #define FSP_DISR_DBG_IN_PROGRESS PPC_BIT32(25) |