xive/p10: Activate split mode for PHB ESBs when PQ_disable is available

1/3rd of the cache is reserved for PHB ESBs and the rest to IPIs.
This is sufficient to keep all the PHB ESBs in cache and avoid ESB
cache misses during IO interrupt processing.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>

1 files changed, 25 insertions, 0 deletions

diff --git a/hw/xive2.c b/hw/xive2.c
index 6ce7027..88f2ae7 100644
--- a/hw/xive2.c
+++ b/hw/xive2.c
@@ -1601,6 +1601,29 @@ static bool xive_cfg_save_restore(struct xive *x)
 	return !!(x->config & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE);
 }
 
+/*
+ * When PQ_disable is available, configure the ESB cache to improve
+ * performance for PHB ESBs.
+ *
+ * split_mode :
+ *   1/3rd of the cache is reserved for PHB ESBs and the rest to
+ *   IPIs. This is sufficient to keep all the PHB ESBs in cache and
+ *   avoid ESB cache misses during IO interrupt processing.
+ */
+static void xive_config_esb_cache(struct xive *x)
+{
+	uint64_t val = xive_regr(x, VC_ESBC_CFG);
+
+	if (xive_has_cap(x, CQ_XIVE_CAP_PHB_PQ_DISABLE)) {
+		val |= VC_ESBC_CFG_SPLIT_MODE;
+		xive_dbg(x, "ESB cache configured with split mode. "
+			 "VC_ESBC_CFG=%016llx\n", val);
+	} else
+		val &= ~VC_ESBC_CFG_SPLIT_MODE;
+
+	xive_regw(x, VC_ESBC_CFG, val);
+}
+
 static void xive_config_fused_core(struct xive *x)
 {
 	uint64_t val = xive_regr(x, TCTXT_CFG);
@@ -1716,6 +1739,8 @@ static bool xive_config_init(struct xive *x)
 
 	xive_config_fused_core(x);
 
+	xive_config_esb_cache(x);
+
 	xive_config_reduced_priorities_fixup(x);
 
 	return true;