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| author | Michael Neuling <mikey@neuling.org> | 2021-08-04 12:51:29 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:29:53 +0530 |
| commit | c226e8bade288835fd78dad3f3751ae322819139 (patch) | |
| tree | 3da70d6c6112c4cfb891908a42f8fec15e96cc3b /hw | |
| parent | 3e0d7c07b7c5d627d81f7386f6f2a9027b84faf6 (diff) | |
| download | skiboot-c226e8bade288835fd78dad3f3751ae322819139.zip skiboot-c226e8bade288835fd78dad3f3751ae322819139.tar.gz skiboot-c226e8bade288835fd78dad3f3751ae322819139.tar.bz2 | |
phb5: Enable Gen5
Registers for Gen5 have been initialized in a previous patch. So let's
activate it!
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/phb4.c | 12 |
1 files changed, 8 insertions, 4 deletions
@@ -3008,12 +3008,16 @@ static int64_t phb4_poll_link(struct pci_slot *slot) static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) { - unsigned int max_link_speed; + unsigned int max_link_speed, hw_max_link_speed; struct proc_chip *chip; chip = get_chip(p->chip_id); + hw_max_link_speed = 4; + if (is_phb5()) + hw_max_link_speed = 5; + /* Priority order: NVRAM -> dt -> GEN3 dd2.00 -> GEN4 */ - max_link_speed = 4; + max_link_speed = hw_max_link_speed; if (p->rev == PHB4_REV_NIMBUS_DD20 && ((0xf & chip->ec_level) == 0) && chip->ec_rev == 0) max_link_speed = 3; @@ -3033,8 +3037,8 @@ static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) } if (pcie_max_link_speed) max_link_speed = pcie_max_link_speed; - if (max_link_speed > 4) /* clamp to 4 */ - max_link_speed = 4; + if (max_link_speed > hw_max_link_speed) + max_link_speed = hw_max_link_speed; return max_link_speed; } |