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| author | Oliver O'Halloran <oohall@gmail.com> | 2021-08-04 12:50:41 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 11:51:25 +0530 |
| commit | b306050c1e9348972a4f7588bacbb52422d9731c (patch) | |
| tree | eb771a3d4033a653d8d64b49131e94be6c0a61c8 /hw | |
| parent | 891ed8df672ddc3a38b4629aa4087f9930e1669d (diff) | |
| download | skiboot-b306050c1e9348972a4f7588bacbb52422d9731c.zip skiboot-b306050c1e9348972a4f7588bacbb52422d9731c.tar.gz skiboot-b306050c1e9348972a4f7588bacbb52422d9731c.tar.bz2 | |
hw/p8-i2c: Add POWER10 support
Early P8s didn't have the I2C interrupt, but all the subsequent chips
have one. Flip the interrupt support checking so the old chips are the
special case rather than having to add a new entry for every new chip.
P10 added several additional flag registers and moved the existing
flag register. The actual data bits have not changed so the existing
handshake protocol between the OCC and OPAL works just fine.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/p8-i2c.c | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 6e24c3e..4581585 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -315,21 +315,15 @@ static bool p8_i2c_has_irqs(struct p8_i2c_master *master) * DD2.0. When operating without interrupts, we need to bump the * timeouts as we rely solely on the polls from Linux which can * be up to 2s apart ! - * - * Also we don't have interrupts for the Centaur i2c. */ - switch (chip->type) { - case PROC_CHIP_P8_MURANO: + if (proc_gen >= proc_gen_p9) + return true; + else if (chip->type == PROC_CHIP_P8_MURANO) return chip->ec_level >= 0x21; - case PROC_CHIP_P8_VENICE: + else if (chip->type == PROC_CHIP_P8_VENICE) return chip->ec_level >= 0x20; - case PROC_CHIP_P8_NAPLES: - case PROC_CHIP_P9_NIMBUS: - case PROC_CHIP_P9_CUMULUS: - return true; - default: - return false; - } + + return true; } static int p8_i2c_enable_irqs(struct p8_i2c_master *master) @@ -928,8 +922,8 @@ static int p8_i2c_check_initial_status(struct p8_i2c_master_port *port) */ static bool occ_uses_master(struct p8_i2c_master *master) { - /* OCC uses I2CM Engines 1,2 and 3, only on POWER9 */ - if (master->type == I2C_POWER8 && proc_gen == proc_gen_p9) + /* OCC uses I2CM Engines 1,2 and 3, only on POWER9/10 */ + if (master->type == I2C_POWER8 && proc_gen >= proc_gen_p9) return master->engine_id >= 1; return false; @@ -1591,7 +1585,12 @@ void p8_i2c_init(void) int i; /* setup the handshake reg */ - occflg = 0x6C08A; + if (proc_gen <= proc_gen_p9) + occflg = 0x6C08A; + else if (proc_gen == proc_gen_p10) + occflg = 0x6C0AC; + else + return; prlog(PR_INFO, "I2C: OCC flag reg: %x\n", occflg); |