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| author | Andrew Donnellan <ajd@linux.ibm.com> | 2020-04-15 17:29:16 +1000 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2020-05-26 14:30:29 +1000 |
| commit | 75198f668911830bb5df27da59786199eac2e47c (patch) | |
| tree | ea1e51cc662123742cf43fd11b3b319c2f61a312 /hw | |
| parent | 482f18adf21eeb5f6ce2a93334725509a8f6f0cd (diff) | |
| download | skiboot-75198f668911830bb5df27da59786199eac2e47c.zip skiboot-75198f668911830bb5df27da59786199eac2e47c.tar.gz skiboot-75198f668911830bb5df27da59786199eac2e47c.tar.bz2 | |
hw/phys-map: Fix OCAPI_MEM BAR values
The comment next to the OCAPI_MEM entries in the Nimbus phys-map claims
that we are "varying the upper 2 bits of the group ID" for each OpenCAPI
link, as matches the chip address extension mask that will be set by future
versions of Hostboot.
The actual entries, on the other hand, vary the *lower* 2 bits of the group
ID. Whoops.
This didn't appear to cause us problems on the specific machines that we
had access to at the time, but now that this is being tested a bit harder
it's crashing machines...
Fixes: bc72973d13215 ("hw/npu2-opencapi: Support multiple LPC devices")
Cc: Frederic Barrat <fbarrat@linux.ibm.com>
Reported-by: Wael El-Essawy <welessa@us.ibm.com>
Reported-by: Milton Miller <miltonm@us.ibm.com>
Reported-by: Jenny Huynh <jhuynh@us.ibm.com>
Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/phys-map.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/phys-map.c b/hw/phys-map.c index ad04173..2c4d8e4 100644 --- a/hw/phys-map.c +++ b/hw/phys-map.c @@ -53,9 +53,9 @@ static const struct phys_map_entry phys_map_table_nimbus[] = { * We don't currently support >4TB ranges. */ { OCAPI_MEM, 0, 0x0002000000000000ull, 0x0000040000000000ull }, - { OCAPI_MEM, 1, 0x0002200000000000ull, 0x0000040000000000ull }, - { OCAPI_MEM, 2, 0x0002400000000000ull, 0x0000040000000000ull }, - { OCAPI_MEM, 3, 0x0002600000000000ull, 0x0000040000000000ull }, + { OCAPI_MEM, 1, 0x0002800000000000ull, 0x0000040000000000ull }, + { OCAPI_MEM, 2, 0x0003000000000000ull, 0x0000040000000000ull }, + { OCAPI_MEM, 3, 0x0003800000000000ull, 0x0000040000000000ull }, /* 0 TB offset @ MMIO 0x0006000000000000ull */ { PHB4_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull }, |