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| author | Cédric Le Goater <clg@kaod.org> | 2021-08-07 09:38:19 +0200 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-18 16:35:39 +0530 |
| commit | de7141b5e5598633385756cced6a3a499571ab24 (patch) | |
| tree | 41efc8e0022ed297c36c08b0c9146b183e788baf /hw | |
| parent | 820d43c0a7751e75a8830561f35535dfffd522bd (diff) | |
| download | skiboot-de7141b5e5598633385756cced6a3a499571ab24.zip skiboot-de7141b5e5598633385756cced6a3a499571ab24.tar.gz skiboot-de7141b5e5598633385756cced6a3a499571ab24.tar.bz2 | |
xive/p10: Fix xive_special_cache_check when DEBUG=1
The special cache check done when skiboot is compiled with DEBUG is
incompatible with Automatic Context Save and Restore.
Random data is written in the NVP to check that cache updates are
correct but this can lead to a checkstop raised by the XIVE interrupt
controller. When the NVP Valid (0) bit, the hardware controlled H (7)
bit, and the Checked Out bit (45) are all ones at the same time, the
HW thinks that the NVP entry is checked out by a thread and does not
allow the cache write to occur.
Make sure that the valid bit is not set on the NVP.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/xive2.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -25,7 +25,6 @@ /* Verbose debug */ #undef XIVE_VERBOSE_DEBUG -#undef DEBUG /* Extra debug options used in debug builds */ #ifdef DEBUG @@ -2938,6 +2937,7 @@ static void xive_special_cache_check(struct xive *x, uint32_t blk, uint32_t idx) struct xive_nvp *vp_m = xive_get_vp(x, idx); memset(vp_m, (~i) & 0xff, sizeof(*vp_m)); + vp_m->w0 = xive_set_field32(NVP_W0_VALID, vp_m->w0, 0); sync(); vp.w1 = (i << 16) | i; assert(!xive_nxc_cache_update(x, blk, idx, &vp, true)); |