diff options
| author | Russell Currey <ruscur@russell.cc> | 2016-10-12 14:56:25 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-10-12 16:45:53 +1100 |
| commit | 5ac71c9b9f7a6c7dc909bdcf121f8d1d11a10dc2 (patch) | |
| tree | 9837295ab9513379212e79e2bb7a40c462527261 /hw | |
| parent | d8b7ad297887f681bef06df684acb8ea97171bda (diff) | |
| download | skiboot-5ac71c9b9f7a6c7dc909bdcf121f8d1d11a10dc2.zip skiboot-5ac71c9b9f7a6c7dc909bdcf121f8d1d11a10dc2.tar.gz skiboot-5ac71c9b9f7a6c7dc909bdcf121f8d1d11a10dc2.tar.bz2 | |
pci: Avoid hot resets at boot time
In the PCI post-fundamental reset code, a hot reset is performed at the
end. This is causing issues at boot time as a reset signal is being sent
downstream before the links are up, which is causing issues on adapters
behind switches. No errors result in skiboot, but the adapters are not
usable in Linux as a result.
Hot resets also occur in the FSP platform-specific code for conventional
PCI slots, which could cause issues.
This patch fixes some adapters not being configurable in Linux on some
systems. The issue was not present in skiboot 5.2.x.
Cc: stable # 5.3.x
Signed-off-by: Russell Currey <ruscur@russell.cc>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/p7ioc-phb.c | 4 | ||||
| -rw-r--r-- | hw/phb3.c | 4 | ||||
| -rw-r--r-- | hw/phb4.c | 8 |
3 files changed, 4 insertions, 12 deletions
diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c index d2a18a3..1f1b362 100644 --- a/hw/p7ioc-phb.c +++ b/hw/p7ioc-phb.c @@ -2234,8 +2234,8 @@ static int64_t p7ioc_freset(struct pci_slot *slot) return slot->ops.pfreset(slot); } - pci_slot_set_state(slot, P7IOC_SLOT_HRESET_START); - return slot->ops.hreset(slot); + pci_slot_set_state(slot, P7IOC_SLOT_LINK_START); + return slot->ops.poll_link(slot); default: PHBERR(p, "FRESET: Unexpected slot state %08x\n", slot->state); @@ -2262,8 +2262,8 @@ static int64_t phb3_pfreset(struct pci_slot *slot) /* CAPP FPGA requires 1s to flash before polling link */ return pci_slot_set_sm_timeout(slot, secs_to_tb(1)); case PHB3_SLOT_PFRESET_DEASSERT_DELAY: - pci_slot_set_state(slot, PHB3_SLOT_HRESET_START); - return slot->ops.hreset(slot); + pci_slot_set_state(slot, PHB3_SLOT_LINK_START); + return slot->ops.poll_link(slot); default: PHBERR(p, "Unexpected slot state %08x\n", slot->state); } @@ -1951,16 +1951,8 @@ static int64_t phb4_pfreset(struct pci_slot *slot) /* CAPP FPGA requires 1s to flash before polling link */ return pci_slot_set_sm_timeout(slot, secs_to_tb(1)); case PHB4_SLOT_PFRESET_DEASSERT_DELAY: -#if 0 /* PHB3 does a Hreset here. It's unnecessary I think and it's - * causing problems with the simulator croc model so don't do - * it until I figure out Gavin's reasons - */ - pci_slot_set_state(slot, PHB4_SLOT_HRESET_START); - return slot->ops.hreset(slot); -#else pci_slot_set_state(slot, PHB4_SLOT_LINK_START); return slot->ops.poll_link(slot); -#endif default: PHBERR(p, "Unexpected slot state %08x\n", slot->state); } |