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| author | Reza Arbab <arbab@linux.ibm.com> | 2019-06-07 11:08:30 -0500 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-06-13 11:32:52 +1000 |
| commit | d4f2f77377dab27eaf792aa089090bcdd953a5cc (patch) | |
| tree | 2ac0010ae5980c453006a3daea77cc7858a1e7e8 /hw | |
| parent | 3386550f51745c618eb8936090699becf4dd0775 (diff) | |
| download | skiboot-d4f2f77377dab27eaf792aa089090bcdd953a5cc.zip skiboot-d4f2f77377dab27eaf792aa089090bcdd953a5cc.tar.gz skiboot-d4f2f77377dab27eaf792aa089090bcdd953a5cc.tar.bz2 | |
npu2: Purge cache when resetting a GPU
After putting all a GPU's links in reset, do a cache purge in case we
have CPU cache lines belonging to the now-unaccessible GPU memory.
Fixes: 68d11e4460ec ("npu2: Reset NVLinks when resetting a GPU")
Cc: skiboot-stable@lists.ozlabs.org
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/npu2.c | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -561,6 +561,8 @@ static int64_t npu2_gpu_bridge_sec_bus_reset(void *dev, gpu = list_top(&pd->children, struct pci_device, link); if (gpu && (*data & PCI_CFG_BRCTL_SECONDARY_RESET)) { + int64_t rc; + dt_for_each_compatible(dt_root, np, "ibm,power9-npu-pciex") { npphb = pci_get_phb(dt_prop_get_cell(np, "ibm,opal-phbid", 1)); @@ -574,6 +576,10 @@ static int64_t npu2_gpu_bridge_sec_bus_reset(void *dev, npu2_dev_procedure_reset(ndev); } } + + rc = purge_l2_l3_caches(); + if (rc) + return rc; } return OPAL_PARTIAL; |