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author | Oliver O'Halloran <oohall@gmail.com> | 2017-12-05 14:19:19 +1100 |
---|---|---|
committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-12-11 19:30:46 -0600 |
commit | 5bb9d6f1e7dc0e38beb1db8f9f032a926310beac (patch) | |
tree | 09cdae2bd55bf99e284d1b26c7e27d42023f7ac4 /hw | |
parent | 22df7a1c73c933195c2a06418ebb3434c6e6b506 (diff) | |
download | skiboot-5bb9d6f1e7dc0e38beb1db8f9f032a926310beac.zip skiboot-5bb9d6f1e7dc0e38beb1db8f9f032a926310beac.tar.gz skiboot-5bb9d6f1e7dc0e38beb1db8f9f032a926310beac.tar.bz2 |
chiptod: Keep boot timestamps contiguous
Currently we reset the timebase value to (almost) zero when
synchronising the timebase of each chip to the Chip TOD network which
results in this:
[ 42.374813167,5] CPU: All 80 processors called in...
[ 2.222791151,5] FLASH: Found system flash: Macronix MXxxL51235F id:0
[ 2.222977933,5] BT: Interface initialized, IO 0x00e4
This patch modifies the chiptod_init() process to use the current
timebase value rather than resetting it to zero. This results in the
timestamps remaining contigious from the start of hostboot until
the petikernel starts. e.g.
[ 70.188811484,5] CPU: All 144 processors called in...
[ 72.458004252,5] FLASH: Found system flash: id:0
[ 72.458147358,5] BT: Interface initialized, IO 0x00e4
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/chiptod.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/hw/chiptod.c b/hw/chiptod.c index b9e4774..cacc273 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -120,9 +120,6 @@ #define LOCAL_CORE_FIR 0x0104000C #define LFIR_SWITCH_COMPLETE PPC_BIT(18) -/* Magic TB value. One step cycle ahead of sync */ -#define INIT_TB 0x000000000001ff0 - /* Number of iterations for the various timeouts */ #define TIMEOUT_LOOPS 20000000 @@ -775,6 +772,7 @@ static void chiptod_reset_tod_errors(void) static void chiptod_sync_master(void *data) { + uint64_t initial_tb_value; bool *result = data; prlog(PR_DEBUG, "Master sync on CPU PIR 0x%04x...\n", @@ -824,8 +822,17 @@ static void chiptod_sync_master(void *data) goto error; } + /* + * Load the master's current timebase value into the Chip TOD + * network. This is so we have sane timestamps across the whole + * IPL process. The Chip TOD documentation says that the loaded + * value needs to be one STEP before a SYNC. In other words, + * set the low bits to 0x1ff0. + */ + initial_tb_value = (mftb() & ~0x1fff) | 0x1ff0; + /* Chip TOD load initial value */ - if (xscom_writeme(TOD_CHIPTOD_LOAD_TB, INIT_TB)) { + if (xscom_writeme(TOD_CHIPTOD_LOAD_TB, initial_tb_value)) { prerror("XSCOM error setting init TB\n"); goto error; } |