diff options
author | Russell Currey <ruscur@russell.cc> | 2015-11-09 15:29:40 +1100 |
---|---|---|
committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-01-12 15:39:26 +1100 |
commit | d67d79a69dd73ee8d01324c4f62707f06e904050 (patch) | |
tree | 51b1fe17e2381c60d14f112cb65b79c37091b952 /hw | |
parent | 089082171fed646296313933602d38493eae2982 (diff) | |
download | skiboot-d67d79a69dd73ee8d01324c4f62707f06e904050.zip skiboot-d67d79a69dd73ee8d01324c4f62707f06e904050.tar.gz skiboot-d67d79a69dd73ee8d01324c4f62707f06e904050.tar.bz2 |
nvlink: Set a bit in config space to indicate a real PCI device was bound
The version was already set (somewhat obscurely), that has been refactored and the version incremented as per the following patch (which supercedes the previous):
Signed-off-by: Russell Currey <ruscur@russell.cc>
Acked-By: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/npu.c | 31 |
1 files changed, 23 insertions, 8 deletions
@@ -111,6 +111,15 @@ static struct npu_dev_cap *npu_dev_find_capability(struct npu_dev *dev, uint16_t id); +#define OPAL_NPU_VERSION 0x02 + +#define PCIE_CAP_START 0x40 +#define PCIE_CAP_END 0x80 +#define VENDOR_CAP_START 0x80 +#define VENDOR_CAP_END 0x90 + +#define VENDOR_CAP_PCI_DEV_OFFSET 0x0d + /* PCI config raw accessors */ #define NPU_DEV_CFG_NORMAL_RD(d, o, s, v) \ npu_dev_cfg_read_raw(d, NPU_DEV_CFG_NORMAL, o, s, v) @@ -546,6 +555,9 @@ static void npu_dev_bind_pci_dev(struct npu_dev *dev) dev->pd = pci_walk_dev(phb, __npu_dev_bind_pci_dev, dev); if (dev->pd) { dev->phb = phb; + /* Found the device, set the bit in config space */ + NPU_DEV_CFG_INIT_RO(dev, VENDOR_CAP_START + + VENDOR_CAP_PCI_DEV_OFFSET, 1, 0x01); return; } } @@ -1194,11 +1206,12 @@ static void npu_dev_populate_vendor_cap(struct npu_dev_cap *cap) { struct npu_dev *dev = cap->dev; uint32_t offset = cap->start; - uint32_t val; + uint8_t val; - /* Add version and length information */ - val = (cap->end - cap->start) | 0x1 << 8; - NPU_DEV_CFG_INIT_RO(dev, offset + 2, 4, val); + /* Add length and version information */ + val = cap->end - cap->start; + NPU_DEV_CFG_INIT_RO(dev, offset + 2, 1, val); + NPU_DEV_CFG_INIT_RO(dev, offset + 3, 1, OPAL_NPU_VERSION); offset += 4; /* Defaults when the trap can't handle the read/write (eg. due @@ -1212,7 +1225,7 @@ static void npu_dev_populate_vendor_cap(struct npu_dev_cap *cap) npu_dev_procedure_write); offset += 8; - NPU_DEV_CFG_INIT_RO(dev, offset, 4, dev->index); + NPU_DEV_CFG_INIT_RO(dev, offset, 1, dev->index); } static void npu_dev_populate_pcie_cap(struct npu_dev_cap *cap) @@ -1229,7 +1242,7 @@ static void npu_dev_populate_pcie_cap(struct npu_dev_cap *cap) } /* Sanity check on spanned registers */ - if ((cap->end - cap->start) < 0x40) { + if ((cap->end - cap->start) < PCIE_CAP_START) { prlog(PR_NOTICE, "%s: Invalid reg region [%x, %x] for cap %d\n", __func__, cap->start, cap->end, cap->id); return; @@ -1352,11 +1365,13 @@ static void npu_dev_create_capabilities(struct npu_dev *dev) /* PCI express capability */ npu_dev_create_capability(dev, npu_dev_populate_pcie_cap, - PCI_CFG_CAP_ID_EXP, 0x40, 0x80); + PCI_CFG_CAP_ID_EXP, PCIE_CAP_START, + PCIE_CAP_END); /* Vendor specific capability */ npu_dev_create_capability(dev, npu_dev_populate_vendor_cap, - PCI_CFG_CAP_ID_VENDOR, 0x80, 0x90); + PCI_CFG_CAP_ID_VENDOR, VENDOR_CAP_START, + VENDOR_CAP_END); } static void npu_dev_create_cfg(struct npu_dev *dev) |