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| author | Michael Neuling <mikey@neuling.org> | 2017-10-23 19:44:07 +1100 |
|---|---|---|
| committer | Michael Neuling <mikey@neuling.org> | 2017-10-23 20:40:23 +1100 |
| commit | 379d745cbf8b5af3d1cdfcfb172b169e157d09a5 (patch) | |
| tree | 997887789473e618bdc3aab99f1b79669a136e7a /hw | |
| parent | 154873b795d44709375a4b843529004e44d6b2ec (diff) | |
| download | skiboot-379d745cbf8b5af3d1cdfcfb172b169e157d09a5.zip skiboot-379d745cbf8b5af3d1cdfcfb172b169e157d09a5.tar.gz skiboot-379d745cbf8b5af3d1cdfcfb172b169e157d09a5.tar.bz2 | |
phb4: Fix GEN3 for DD2.00
In this fix:
62ac7631ae phb4: Fix PCIe GEN4 on DD2.1 and above
We fixed DD2.1 GEN4 but broke DD2.00 as GEN3.
This fixes DD2.00 back to GEN3. This time for sure!
Signed-off-by: Michael Neuling <mikey@neuling.org>
Tested-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/phb4.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -4900,7 +4900,7 @@ static void phb4_create(struct dt_node *np) if (p->rev == PHB4_REV_NIMBUS_DD10) p->max_link_speed = 2; if (p->rev == PHB4_REV_NIMBUS_DD20 && - chip->ec_level == 0 && chip->ec_rev == 0) + ((0xf & chip->ec_level) == 0) && chip->ec_rev == 0) p->max_link_speed = 3; if (dt_has_node_property(np, "ibm,max-link-speed", NULL)) p->max_link_speed = dt_prop_get_u32(np, "ibm,max-link-speed"); |