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authorMichael Neuling <mikey@neuling.org>2017-09-21 17:23:18 +1000
committerStewart Smith <stewart@linux.vnet.ibm.com>2017-09-27 23:02:52 -0500
commit1c3f583bb767b1af43478c682b665b224b69b38e (patch)
tree0a616a589dc6f831a7970bdf36d5dfddd7e569f3 /hw
parentdceed210a2bd2c4031e41d78548e6fc1f37d8f6f (diff)
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phb4: Update link training documentation
We added degraded link retries in: 3f936bae97 phb4: Retrain link if degraded but forgot to update the documentation. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/phb4.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/hw/phb4.c b/hw/phb4.c
index 5e5f50f..e929b15 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -82,6 +82,14 @@
* o Once we leave here, much harder to recover from errors
*
* Step 9:
+ * - Check for optimised link for directly attached devices:
+ * o Wait for CRS (so we can read device config space)
+ * o Check chip and device are in whitelist. if not, Goto Step 10
+ * o If trained link speed is degraded, retry -> Goto Step 2
+ * o If trained link width is degraded, retry -> Goto Step 2
+ * o If still degraded after 3 retries. Give up, Goto Step 10.
+ *
+ * Step 10:
* - PHB good, start probing config space.
* o core/pci.c: pci_reset_phb() -> pci_scan_phb()
*/