opal/hmi: Workaround Power9 hw logic bug for couple of TFMR TB errors.

Add a workaround for a HW logic bug in Power9 where TB residue and HDEC
parity errors cleared by one thread aren't visible to other threads of same
core. The TB reside and HDEC parity error are reported through TFMR bit 45
and 26 respectively. If any of the thread from the core clears the TFMR bit
26 and 45, only thread 0 is able to see that errors are cleared but rest of
the threads 1, 2 and 3 do not see those as cleared.  This causes TB error
recovery to fail for TB residue and HDEC parity errors. TFMR is per core
register and any changes made by a one thread should be visible by other
threads of the same core.

On TB residue error (TFMR bit 45), TB goes into invalid state. Hence avoid
handling/clearing TB residue error if TB is valid and running. Use TFMR bit 41
to check validity of TB state.

For HDEC parity  error (TFMR bit 26), check for other errors on TFMR register
and ignore the pre-recovery for HDEC parity error. If TFMR has any other
TB error bits set alongwith HDEC parity error we can safely ignore handling
of HDEC parity error. Also, while clearing HDEC parity error bit from TFMR,
allow only thread 0 to clear it.

Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

1 files changed, 27 insertions, 0 deletions

diff --git a/hw/chiptod.c b/hw/chiptod.c
index 1dd1b26..b9e4774 100644
--- a/hw/chiptod.c
+++ b/hw/chiptod.c
@@ -1478,6 +1478,7 @@ int chiptod_recover_tb_errors(void)
 {
 	uint64_t tfmr;
 	int rc = -1;
+	int thread_id;
 
 	if (chiptod_primary < 0)
 		return 0;
@@ -1503,6 +1504,17 @@ int chiptod_recover_tb_errors(void)
 	tfmr = mfspr(SPR_TFMR);
 
 	/*
+	 * Workaround for HW logic bug in Power9
+	 * Even after clearing TB residue error by one thread it does not
+	 * get reflected to other threads on same core.
+	 * Check if TB is already valid and skip the checking of TB errors.
+	 */
+
+	if ((proc_gen == proc_gen_p9) && (tfmr & SPR_TFMR_TB_RESIDUE_ERR)
+						&& (tfmr & SPR_TFMR_TB_VALID))
+		goto skip_tb_error_clear;
+
+	/*
 	 * Check for TB errors.
 	 * On Sync check error, bit 44 of TFMR is set. Check for it and
 	 * clear it.
@@ -1525,6 +1537,7 @@ int chiptod_recover_tb_errors(void)
 		}
 	}
 
+skip_tb_error_clear:
 	/*
 	 * Check for TOD sync check error.
 	 * On TOD errors, bit 51 of TFMR is set. If this bit is on then we
@@ -1559,6 +1572,20 @@ int chiptod_recover_tb_errors(void)
 	}
 
 	/*
+	 * Workaround for HW logic bug in power9.
+	 * In idea case (without the HW bug) only one thread from the core
+	 * would have fallen through tfmr_recover_non_tb_errors() to clear
+	 * HDEC parity error on TFMR.
+	 *
+	 * Hence to achieve same behavior, allow only thread 0 to clear the
+	 * HDEC parity error. And for rest of the threads just reset the bit
+	 * to avoid other threads to fall through tfmr_recover_non_tb_errors().
+	 */
+	thread_id = cpu_get_thread_index(this_cpu());
+	if ((proc_gen == proc_gen_p9) && thread_id)
+		tfmr &= ~SPR_TFMR_HDEC_PARITY_ERROR;
+
+	/*
 	 * Now that TB is running, check for TFMR non-TB errors.
 	 */
 	if ((tfmr & SPR_TFMR_HDEC_PARITY_ERROR) ||