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author | Michael Neuling <mikey@neuling.org> | 2017-09-21 17:23:18 +1000 |
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committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-09-27 23:02:52 -0500 |
commit | 1c3f583bb767b1af43478c682b665b224b69b38e (patch) | |
tree | 0a616a589dc6f831a7970bdf36d5dfddd7e569f3 /hw | |
parent | dceed210a2bd2c4031e41d78548e6fc1f37d8f6f (diff) | |
download | skiboot-1c3f583bb767b1af43478c682b665b224b69b38e.zip skiboot-1c3f583bb767b1af43478c682b665b224b69b38e.tar.gz skiboot-1c3f583bb767b1af43478c682b665b224b69b38e.tar.bz2 |
phb4: Update link training documentation
We added degraded link retries in:
3f936bae97 phb4: Retrain link if degraded
but forgot to update the documentation.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/phb4.c | 8 |
1 files changed, 8 insertions, 0 deletions
@@ -82,6 +82,14 @@ * o Once we leave here, much harder to recover from errors * * Step 9: + * - Check for optimised link for directly attached devices: + * o Wait for CRS (so we can read device config space) + * o Check chip and device are in whitelist. if not, Goto Step 10 + * o If trained link speed is degraded, retry -> Goto Step 2 + * o If trained link width is degraded, retry -> Goto Step 2 + * o If still degraded after 3 retries. Give up, Goto Step 10. + * + * Step 10: * - PHB good, start probing config space. * o core/pci.c: pci_reset_phb() -> pci_scan_phb() */ |