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author | Alistair Popple <alistair@popple.id.au> | 2017-06-21 16:31:07 +1000 |
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committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-06-21 18:00:09 +1000 |
commit | a2df920ec740f3ada4a75748aa3420a449d0cc41 (patch) | |
tree | ee9250657ab2773fb750d44ffbc0364bcf8e347c /hw | |
parent | 73e1e8a727a9e7179719eb7844bd4248d9890114 (diff) | |
download | skiboot-a2df920ec740f3ada4a75748aa3420a449d0cc41.zip skiboot-a2df920ec740f3ada4a75748aa3420a449d0cc41.tar.gz skiboot-a2df920ec740f3ada4a75748aa3420a449d0cc41.tar.bz2 |
hw/npu2.c: Fix device aperture calculation
The POWER9 NPU2 implements an address compression scheme to compress 56-bit P9
physical addresses to 47-bit GPU addresses. System software needs to know both
addresses, unfortunately the calculation of the compressed address was
incorrect. Fix it here.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/npu2.c | 6 |
1 files changed, 4 insertions, 2 deletions
@@ -542,8 +542,10 @@ static void npu2_dn_fixup_gmb(struct dt_node *pd_dn, struct npu2_dev *ndev) assert(mem_dn); dt_add_property_cells(pd_dn, "memory-region", mem_dn->phandle); - gta = ((gpu_base >> 42) & 0x1) << 41; - gta |= ((gpu_base >> 45) & 0x3) << 42; + /* Coral mode address compression. This is documented in Figure 3.5 + * "P9->GPU RA Compression (Coral) of the NPU2 workbook". */ + gta = ((gpu_base >> 42) & 0x1) << 42; + gta |= ((gpu_base >> 45) & 0x3) << 43; gta |= ((gpu_base >> 49) & 0x3) << 45; gta |= gpu_base & ((1UL << 43) - 1); |