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authorChristophe Lombard <clombard@linux.vnet.ibm.com>2017-06-13 14:21:22 +0200
committerStewart Smith <stewart@linux.vnet.ibm.com>2017-06-19 17:20:55 +1000
commit71de2375d28d8dba3b50f4857540bc68da3e5856 (patch)
tree0a57c66735a0bc93b8f2d60f36512c4bfb47f3a4 /hw
parente50764d4f2b11fc9e9fe0b2fd0a4617b32593bfa (diff)
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capi: Handle HMI events
Find the CAPP on the chip associated with the HMI event for PHB4. The recovery mode (re-initialization of the capp, resume of functional operations) is only available with P9 DD2. A new patch will be provided to support this feature. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/capp.c9
-rw-r--r--hw/phb3.c35
-rw-r--r--hw/phb4.c33
3 files changed, 77 insertions, 0 deletions
diff --git a/hw/capp.c b/hw/capp.c
index ae79b0f..28a0a4e 100644
--- a/hw/capp.c
+++ b/hw/capp.c
@@ -35,6 +35,7 @@ static struct {
#define CAPP_UCODE_MAX_SIZE 0x20000
struct lock capi_lock = LOCK_UNLOCKED;
+struct capp_ops capi_ops = { NULL };
bool capp_ucode_loaded(struct proc_chip *chip, unsigned int index)
{
@@ -229,3 +230,11 @@ int64_t capp_load_ucode(unsigned int chip_id, uint32_t opal_id,
return OPAL_SUCCESS;
}
+
+int64_t capp_get_info(int chip_id, struct phb *phb, struct capp_info *info)
+{
+ if (capi_ops.get_capp_info)
+ return capi_ops.get_capp_info(chip_id, phb, info);
+
+ return OPAL_PARAMETER;
+}
diff --git a/hw/phb3.c b/hw/phb3.c
index 7922098..bc04c36 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -3394,6 +3394,38 @@ static int64_t phb3_get_diag_data(struct phb *phb,
return OPAL_SUCCESS;
}
+static int64_t phb3_get_capp_info(int chip_id, struct phb *phb,
+ struct capp_info *info)
+{
+ struct phb3 *p = phb_to_phb3(phb);
+ struct proc_chip *chip = get_chip(p->chip_id);
+ uint32_t offset;
+
+ if (chip_id != p->chip_id)
+ return OPAL_PARAMETER;
+
+ if (!((1 << p->index) & chip->capp_phb3_attached_mask))
+ return OPAL_PARAMETER;
+
+ offset = PHB3_CAPP_REG_OFFSET(p);
+
+ if (PHB3_IS_NAPLES(p)) {
+ if (p->index == 0)
+ info->capp_index = 0;
+ else
+ info->capp_index = 1;
+ } else
+ info->capp_index = 0;
+ info->phb_index = p->index;
+ info->capp_fir_reg = CAPP_FIR + offset;
+ info->capp_fir_mask_reg = CAPP_FIR_MASK + offset;
+ info->capp_fir_action0_reg = CAPP_FIR_ACTION0 + offset;
+ info->capp_fir_action1_reg = CAPP_FIR_ACTION1 + offset;
+ info->capp_err_status_ctrl_reg = CAPP_ERR_STATUS_CTRL + offset;
+
+ return OPAL_SUCCESS;
+}
+
static void phb3_init_capp_regs(struct phb3 *p, bool dma_mode)
{
uint64_t reg;
@@ -3606,6 +3638,9 @@ static int64_t enable_capi_mode(struct phb3 *p, uint64_t pe_number, bool dma_mod
return OPAL_HARDWARE;
}
+ /* set callbacks to handle HMI events */
+ capi_ops.get_capp_info = &phb3_get_capp_info;
+
return OPAL_SUCCESS;
}
diff --git a/hw/phb4.c b/hw/phb4.c
index 27b970a..e56a3f4 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -2762,6 +2762,35 @@ static uint64_t tve_encode_50b_noxlate(uint64_t start_addr, uint64_t end_addr)
return tve;
}
+static int64_t phb4_get_capp_info(int chip_id, struct phb *phb,
+ struct capp_info *info)
+{
+ struct phb4 *p = phb_to_phb4(phb);
+ struct proc_chip *chip = get_chip(p->chip_id);
+ uint32_t offset;
+
+ if (chip_id != p->chip_id)
+ return OPAL_PARAMETER;
+
+ if (!((1 << p->index) & chip->capp_phb4_attached_mask))
+ return OPAL_PARAMETER;
+
+ offset = PHB4_CAPP_REG_OFFSET(p);
+
+ if (p->index == CAPP0_PHB_INDEX)
+ info->capp_index = 0;
+ if (p->index == CAPP1_PHB_INDEX)
+ info->capp_index = 1;
+ info->phb_index = p->index;
+ info->capp_fir_reg = CAPP_FIR + offset;
+ info->capp_fir_mask_reg = CAPP_FIR_MASK + offset;
+ info->capp_fir_action0_reg = CAPP_FIR_ACTION0 + offset;
+ info->capp_fir_action1_reg = CAPP_FIR_ACTION1 + offset;
+ info->capp_err_status_ctrl_reg = CAPP_ERR_STATUS_CTRL + offset;
+
+ return OPAL_SUCCESS;
+}
+
static void phb4_init_capp_regs(struct phb4 *p)
{
uint64_t reg;
@@ -3031,6 +3060,10 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
PHBERR(p, "CAPP: Failed to sync timebase\n");
return OPAL_HARDWARE;
}
+
+ /* set callbacks to handle HMI events */
+ capi_ops.get_capp_info = &phb4_get_capp_info;
+
return OPAL_SUCCESS;
}