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| author | Alistair Popple <alistair@popple.id.au> | 2017-05-05 17:37:15 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-05-10 14:32:22 +1000 |
| commit | fd16aff64d9ad822c3b2d30248c1ea0dcd3159f4 (patch) | |
| tree | a5056880abff0360eb72b97a2827c0ce74fce391 /hw | |
| parent | 5d206f0b23f6765a914b9d35cab2b75bf9dae451 (diff) | |
| download | skiboot-fd16aff64d9ad822c3b2d30248c1ea0dcd3159f4.zip skiboot-fd16aff64d9ad822c3b2d30248c1ea0dcd3159f4.tar.gz skiboot-fd16aff64d9ad822c3b2d30248c1ea0dcd3159f4.tar.bz2 | |
npu2: Do not attempt to initialise non DD1 hardware
There are significant changes to hardware register addresses and
meanings on newer chip revisions making them unlikely to work
correctly with the existing code. Better to fail clearly and early.
Suggested-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/npu2.c | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -1183,6 +1183,7 @@ static void assign_mmio_bars(uint64_t gcid, uint32_t scom, uint64_t reg[2], uint */ static void npu2_probe_phb(struct dt_node *dn) { + struct proc_chip *proc_chip; struct dt_node *np; uint32_t gcid, scom, index, phb_index, links; uint64_t reg[2], mm_win[2]; @@ -1191,6 +1192,12 @@ static void npu2_probe_phb(struct dt_node *dn) /* Retrieve chip id */ path = dt_get_path(dn); gcid = dt_get_chip_id(dn); + assert(proc_chip = get_chip(gcid)); + if ((proc_chip->ec_level & 0xf0) != 0x10) { + prerror("NPU2: unsupported ec level on Chip 0x%x!\n", gcid); + return; + } + index = dt_prop_get_u32(dn, "ibm,npu-index"); phb_index = dt_prop_get_u32(dn, "ibm,phb-index"); links = dt_prop_get_u32(dn, "ibm,npu-links"); |