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author | Christophe Lombard <clombard@linux.vnet.ibm.com> | 2021-10-14 17:57:04 +0200 |
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committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:26:02 +0530 |
commit | 4c1add1fb20fe07b827227ca34f63f176774d51c (patch) | |
tree | 6f191cb95c848d7bbf2268231cc62f7d8719f0d0 /hw | |
parent | 2d89dd334756d19a9ffc3e4c784406177f46c053 (diff) | |
download | skiboot-4c1add1fb20fe07b827227ca34f63f176774d51c.zip skiboot-4c1add1fb20fe07b827227ca34f63f176774d51c.tar.gz skiboot-4c1add1fb20fe07b827227ca34f63f176774d51c.tar.bz2 |
pau: Add support for OpenCAPI Persistent Memory devices.
Lowest Point of Coherency (LPC) memory allows the host to access memory on
an OpenCAPI device.
When the P10 chip accesses memory addresses on the AFU, the Real Address
on the PowerBus must hit a BAR in the PAU such as GPU-Memory BAR. The BAR
defines the range of Real Addresses that represent AFU memory.
The two existing OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE
are used to manage the AFU momory.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/npu-opal.c | 35 | ||||
-rw-r--r-- | hw/npu2-opencapi.c | 18 | ||||
-rw-r--r-- | hw/pau.c | 93 | ||||
-rw-r--r-- | hw/phys-map.c | 7 |
4 files changed, 137 insertions, 16 deletions
diff --git a/hw/npu-opal.c b/hw/npu-opal.c index 2e455dc..1b66857 100644 --- a/hw/npu-opal.c +++ b/hw/npu-opal.c @@ -239,3 +239,38 @@ static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, return OPAL_PARAMETER; } opal_call(OPAL_NPU_TL_SET, opal_npu_tl_set, 5); + +static int64_t opal_npu_mem_alloc(uint64_t phb_id, uint32_t bdfn, + uint64_t size, uint64_t *bar) +{ + struct phb *phb = pci_get_phb(phb_id); + + if (!phb) + return OPAL_PARAMETER; + + if (phb->phb_type == phb_type_npu_v2_opencapi) + return npu2_opencapi_mem_alloc(phb, bdfn, size, bar); + + if (phb->phb_type == phb_type_pau_opencapi) + return pau_opencapi_mem_alloc(phb, bdfn, size, bar); + + return OPAL_PARAMETER; +} +opal_call(OPAL_NPU_MEM_ALLOC, opal_npu_mem_alloc, 4); + +static int64_t opal_npu_mem_release(uint64_t phb_id, uint32_t bdfn) +{ + struct phb *phb = pci_get_phb(phb_id);; + + if (!phb) + return OPAL_PARAMETER; + + if (phb->phb_type == phb_type_npu_v2_opencapi) + return npu2_opencapi_mem_release(phb, bdfn); + + if (phb->phb_type == phb_type_pau_opencapi) + return pau_opencapi_mem_release(phb, bdfn); + + return OPAL_PARAMETER; +} +opal_call(OPAL_NPU_MEM_RELEASE, opal_npu_mem_release, 2); diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index 272f924..8e7bcca 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -2295,18 +2295,13 @@ out: return rc; } -static int64_t opal_npu_mem_alloc(uint64_t phb_id, uint32_t __unused bdfn, - uint64_t size, __be64 *__bar) +int64_t npu2_opencapi_mem_alloc(struct phb *phb, uint32_t __unused bdfn, + uint64_t size, uint64_t *__bar) { - struct phb *phb = pci_get_phb(phb_id); struct npu2_dev *dev; uint64_t bar; int64_t rc; - - if (!phb || phb->phb_type != phb_type_npu_v2_opencapi) - return OPAL_PARAMETER; - dev = phb_to_npu2_dev_ocapi(phb); if (!dev) return OPAL_PARAMETER; @@ -2320,21 +2315,14 @@ static int64_t opal_npu_mem_alloc(uint64_t phb_id, uint32_t __unused bdfn, return rc; } -opal_call(OPAL_NPU_MEM_ALLOC, opal_npu_mem_alloc, 4); -static int64_t opal_npu_mem_release(uint64_t phb_id, uint32_t __unused bdfn) +int64_t npu2_opencapi_mem_release(struct phb *phb, uint32_t __unused bdfn) { - struct phb *phb = pci_get_phb(phb_id); struct npu2_dev *dev; - - if (!phb || phb->phb_type != phb_type_npu_v2_opencapi) - return OPAL_PARAMETER; - dev = phb_to_npu2_dev_ocapi(phb); if (!dev) return OPAL_PARAMETER; return release_mem_bar(dev); } -opal_call(OPAL_NPU_MEM_RELEASE, opal_npu_mem_release, 2); @@ -442,6 +442,99 @@ int64_t pau_opencapi_tl_set(struct phb *phb, uint32_t __unused bdfn, return OPAL_SUCCESS; } +static int64_t pau_opencapi_afu_memory_bars(struct pau_dev *dev, + uint64_t size, + uint64_t *bar) +{ + struct pau *pau = dev->pau; + uint64_t addr, psize; + uint64_t reg, val; + + PAUDEVDBG(dev, "Setup AFU Memory BARs\n"); + + if (dev->memory_bar.enable) { + PAUDEVERR(dev, "AFU memory allocation failed - BAR already in use\n"); + return OPAL_RESOURCE; + } + + phys_map_get(pau->chip_id, OCAPI_MEM, + dev->index, + &addr, &psize); + + if (size > psize) { + PAUDEVERR(dev, "Invalid AFU memory BAR allocation size " + "requested: 0x%llx bytes (limit 0x%llx)\n", + size, psize); + return OPAL_PARAMETER; + } + + if (size < (1 << 30)) + size = 1 << 30; + + dev->memory_bar.enable = true; + dev->memory_bar.addr = addr; + dev->memory_bar.size = size; + + reg = PAU_GPU_MEM_BAR(dev->index); + val = PAU_GPU_MEM_BAR_ENABLE | + PAU_GPU_MEM_BAR_POISON; + val = SETFIELD(PAU_GPU_MEM_BAR_ADDR, val, addr >> 30); + if (!is_pow2(size)) + size = 1ull << (ilog2(size) + 1); + + size = (size >> 30) - 1; + val = SETFIELD(PAU_GPU_MEM_BAR_SIZE, val, size); + pau_write(pau, reg, val); + + reg = PAU_CTL_MISC_GPU_MEM_BAR(dev->index); + pau_write(pau, reg, val); + + reg = PAU_XSL_GPU_MEM_BAR(dev->index); + pau_write(pau, reg, val); + + *bar = addr; + return OPAL_SUCCESS; +} + +int64_t pau_opencapi_mem_alloc(struct phb *phb, uint32_t __unused bdfn, + uint64_t size, uint64_t *bar) +{ + struct pau_dev *dev = pau_phb_to_opencapi_dev(phb); + int64_t rc; + + if (!dev) + return OPAL_PARAMETER; + + if (!opal_addr_valid(bar)) + return OPAL_PARAMETER; + + lock(&dev->pau->lock); + rc = pau_opencapi_afu_memory_bars(dev, size, bar); + + unlock(&dev->pau->lock); + return rc; +} + +int64_t pau_opencapi_mem_release(struct phb *phb, uint32_t __unused bdfn) +{ + struct pau_dev *dev = pau_phb_to_opencapi_dev(phb); + + if (!dev) + return OPAL_PARAMETER; + + lock(&dev->pau->lock); + pau_write(dev->pau, PAU_GPU_MEM_BAR(dev->index), 0ull); + pau_write(dev->pau, PAU_CTL_MISC_GPU_MEM_BAR(dev->index), 0ull); + pau_write(dev->pau, PAU_XSL_GPU_MEM_BAR(dev->index), 0ull); + + dev->memory_bar.enable = false; + dev->memory_bar.addr = 0ull; + dev->memory_bar.size = 0ull; + unlock(&dev->pau->lock); + + return OPAL_SUCCESS; +} + #define CQ_CTL_STATUS_TIMEOUT 10 /* milliseconds */ static int pau_opencapi_set_fence_control(struct pau_dev *dev, diff --git a/hw/phys-map.c b/hw/phys-map.c index 711d626..cfce4ab 100644 --- a/hw/phys-map.c +++ b/hw/phys-map.c @@ -30,7 +30,12 @@ static const struct phys_map_entry phys_map_table_p10[] = { /* System memory upto 4TB minus GPU memory */ { SYSTEM_MEM, 0, 0x0000000000000000ull, 0x0000034000000000ull }, - /* TODO: Figure out GPU memory */ + /* Configure OpenCapi memory as before with the old chips. + * Keep in mind that we would need to rework this by allocating + * a new topology id. + */ + { OCAPI_MEM, 0, 0x0002000000000000ull, 0x0000040000000000ull }, + { OCAPI_MEM, 1, 0x0002040000000000ull, 0x0000040000000000ull }, /* 0 TB offset @ MMIO 0x0006000000000000ull */ { PHB5_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull }, |