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authorChristophe Lombard <clombard@linux.vnet.ibm.com>2021-10-14 17:57:03 +0200
committerVasant Hegde <hegdevasant@linux.vnet.ibm.com>2021-10-19 12:26:02 +0530
commit2d89dd334756d19a9ffc3e4c784406177f46c053 (patch)
treee31c9da1b6a84def34305db432ddca09448dcbfa /hw
parentd5b79b2e9bb63ec18b5b5e4d027d5d1d1b0a4e28 (diff)
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pau: mmio invalidates
The remaining translation mode: OpenCAPI 5.0 with TLBI/SLBI Snooping, is not used due to performance problems caused by the mismatch between the ERAT and Bloom Filter sizes. When the Address Translation Mode requires TLB and SLB Invalidate operations to be initiated using MMIO registers, a set of registers like the following is used: • XTS MMIO ATSD0 LPARID register • XTS MMIO ATSD0 AVA register • XTS MMIO ATSD0 launch register, write access initiates a shoot down • XTS MMIO ATSD0 status register Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/npu-opal.c3
-rw-r--r--hw/pau.c36
2 files changed, 39 insertions, 0 deletions
diff --git a/hw/npu-opal.c b/hw/npu-opal.c
index cf13690..2e455dc 100644
--- a/hw/npu-opal.c
+++ b/hw/npu-opal.c
@@ -52,6 +52,9 @@ static int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
if (phb->phb_type == phb_type_npu_v2)
return npu2_map_lpar(phb, bdf, lparid, lpcr);
+ if (phb->phb_type == phb_type_pau_opencapi)
+ return pau_opencapi_map_atsd_lpar(phb, bdf, lparid, lpcr);
+
return OPAL_PARAMETER;
}
opal_call(OPAL_NPU_MAP_LPAR, opal_npu_map_lpar, 4);
diff --git a/hw/pau.c b/hw/pau.c
index 83cd6fe..9f6a709 100644
--- a/hw/pau.c
+++ b/hw/pau.c
@@ -268,6 +268,29 @@ static void pau_device_detect_fixup(struct pau_dev *dev)
dt_add_property_strings(dn, "ibm,pau-link-type", "unknown");
}
+int64_t pau_opencapi_map_atsd_lpar(struct phb *phb, uint64_t __unused bdf,
+ uint64_t lparid, uint64_t __unused lpcr)
+{
+ struct pau_dev *dev = pau_phb_to_opencapi_dev(phb);
+ struct pau *pau = dev->pau;
+ uint64_t val;
+
+ if (lparid >= PAU_XTS_ATSD_MAX)
+ return OPAL_PARAMETER;
+
+ lock(&pau->lock);
+
+ /* We need to allocate an ATSD per link */
+ val = SETFIELD(PAU_XTS_ATSD_HYP_LPARID, 0ull, lparid);
+ if (!lparid)
+ val |= PAU_XTS_ATSD_HYP_MSR_HV;
+
+ pau_write(pau, PAU_XTS_ATSD_HYP(lparid), val);
+
+ unlock(&pau->lock);
+ return OPAL_SUCCESS;
+}
+
int64_t pau_opencapi_spa_setup(struct phb *phb, uint32_t __unused bdfn,
uint64_t addr, uint64_t PE_mask)
{
@@ -1442,6 +1465,18 @@ static void pau_opencapi_create_phb(struct pau_dev *dev)
pau_opencapi_create_phb_slot(dev);
}
+static void pau_dt_add_mmio_atsd(struct pau_dev *dev)
+{
+ struct dt_node *dn = dev->phb.dt_node;
+ struct pau *pau = dev->pau;
+ uint64_t mmio_atsd[PAU_XTS_ATSD_MAX];
+
+ for (uint32_t i = 0; i < PAU_XTS_ATSD_MAX; i++)
+ mmio_atsd[i] = pau->regs[0] + PAU_XTS_ATSD_LAUNCH(i);
+
+ dt_add_property(dn, "ibm,mmio-atsd", mmio_atsd, sizeof(mmio_atsd));
+}
+
static void pau_opencapi_dt_add_mmio_window(struct pau_dev *dev)
{
struct dt_node *dn = dev->phb.dt_node;
@@ -1508,6 +1543,7 @@ static void pau_opencapi_dt_add_props(struct pau_dev *dev)
dt_add_property_cells(dn, "ibm,opal-num-pes", PAU_MAX_PE_NUM);
dt_add_property_cells(dn, "ibm,opal-reserved-pe", PAU_RESERVED_PE_NUM);
+ pau_dt_add_mmio_atsd(dev);
pau_opencapi_dt_add_mmio_window(dev);
pau_opencapi_dt_add_hotpluggable(dev);
}